• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.2
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• pp.309-314
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• 2008

Analog-to-digital converters(ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental(integrating) data converters(IDCs) provide a solution for such measurement applications, as they retain most of the advantages of conventional $\Delta{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth AC signals over multi-channel is discussed. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.6
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• pp.497-504
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• 2021

This paper presents improvement of the reception noise suppression method during formation flights of aircraft. Since aircraft communication equipment is very important for flight mission and safety to perform the functions of internal/external communications, it is required to implement noise-free, clean communication quality, and transmitting/receiving functions. Therefore, the FTA (Fault Tree Analysis) analysis and failure search were performed on the reception noise, and the internal noise of the intercom that affected the reception noise and the none-transmition phenomenon was identified. We changed the multiple grounds of the intercom to a single ground and applied an improved method of filtering the DC Offset voltage. As a result, the voice quality of the communication system of the aircraft was improved through the reduction of the reception noise during formation flights, and it was verified by ground and flight tests.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.11
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• pp.1806-1812
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• 2016

We propose an interior permanent magnet syhchronous motor (IPMSM) with arc-shape ferrite permanent magnets (PMs) as a substitute for the rare-earth permanent magnet, and determine its optimal design through parametric study. First, we use 2D finite element analysis to analyze 4-poles and 6-slots initial model according to performance requirements and design parameters. The current angle of the maximum average torque considered in the analysis is different compared with the current angle of the minimum torque ripple. Thus, the parametric study for optimal rotor design is performed by varying the thickness and the offset radius of the PMs according to current angle. In particular, a narrow bridge is required in conventional IPMSM for reducing flux leakage; however, the increase in cogging torque in the analysis model saturates the narrow bridge (large offset radius). Therefore, we suggest an appropriate shape considering limiting conditions such as DC link voltage, average torque, torque ripple, and cogging torque taking into account performance requirements.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.155-159
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• 2003

This paper presents fully integrated 5 GHz band low phase noise LC tank VCO. The implemented VCO is tuned by integrated PN diode and tuning rage is $5.01{\sim}5.30$ GHz under $0{\sim}3 V$ control voltage. For good phase noise performance, LC filtering technique, common in Si CMOS process, is used, and to prevent degradation of phase noise performance by collector shot-noise and to reduce power dissipation the HBT is biased at low collector current density bias point. The measured phase noise is -87.8 dBc/Hz at 100 kHz offset frequency and -111.4 dBc/Hz at 1 MHz offset frequency which is good performance. Moreover phase noise is improved by roughly 5 dEc by LC filter. It is the first experimental result in InGaP/GaAs HBT process. The figure of merit of the fabricated VCO with LC filter is -172.1 dBc/Hz. It is the best result among 5 GHz InGaP HBT VCOs. Moreover this work shows lower DC power consumption, higher output power and more fixed output power compared with previous 4, 5 GHz band InGaP HBT VCOs.

• Journal of Broadcast Engineering
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• v.21 no.2
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• pp.261-267
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• 2016

In this paper, Method for the phase distortion compensation timing offset and DC eliminator for the pilot component estimation and removal, transmitted and received signal correlation in the delay scheme DAB interference cancellation based on the same channel for using for estimating the feedback signal based on a between for removal for the timing offset compensation It proposes a repeater. This was applied to the ATSC system. The on-channel repeater of the proposed interference cancellation based on the interference removing capability is improved in interference signal is 20dB greater than the primary transmission signal environment via the return channel estimation and improve performance RFP. Accordingly, it was confirmed by simulation that good signal is sent out with the improvement of the ability of the repeater.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.32-36
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• 2004

In order to achieve high performance vector control, it is essential to measure accurate ac current. The errors generated from current path are inevitable, and they could be divided into two categories: offset error and scaling error. The current data including these errors cause periodic speed ripples which are one and two times of stator electrical frequency respectively. Since these undesirable ripples bring about bad influences to motor driving system, a compensation algorithm must be needed in the control algorithm of the motor drive. In this paper, a new compensation algorithm is proposed. The signal of the integrator output of the d-axis current regulator is chosen and processed to compensate the current measurement errors. The compensation of the current measurement errors is easily implemented to smooth the signal of the integrator output of the d-axis current regulator by subtracting the DC offset value or rescaling the gain of the hall sensor. Therefore, the proposed algorithm has several features: the robustness of the variation of the mechanical parameters, the application of the steady and transient state, the easy implementation, and less computation time.

• Journal of Power Electronics
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• v.16 no.1
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• pp.163-172
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• 2016

The modular multilevel converter (MMC) has been receiving increased attentions in recent years. The new modular multilevel converter is a derivative topology from the traditional MMC in which the number of sub-modules (SMs) necessitated by each phase can be reduced by one. This paper presents a phase-shifted carrier pulse-width modulation (PSC-PWM) for the new MMC with an optimal phase-shifted angle to suppress the harmonics of the output voltage. Further, the harmonic features when the capacitor voltage of the middle SM is selected as two different values are also investigated. Moreover, in order to avoid introducing an unnecessary dc offset current at the ac terminals of the new MMC, a novel capacitor voltage balancing scheme is proposed by adjusting the amplitude of the reference signals rather than the offset. Finally, the validity and effectiveness of the proposed modulation and balancing schemes have been verified by experimental results based on a three-phase prototype of the new MMC.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.492-500
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• 2013

A balanced forward-flyback converter for high efficiency and high power factor using a foward and flyback converter topologies is proposed in this paper. The conventional AC/DC flyback converter can achieve a good power factor but it has the high offset current through the transformer magnetizing inductor, which results in a large core loss and low power conversion efficiency. And, the conventional forward converter can achieve the good power conversion efficiency with the aid of the low core loss but the input current dead zone near zero cross AC input voltage deteriorates the power factor. On the other hand, since the proposed converter can operate as the forward and flyback converters during switch turn-on and turn-off periods, respectively, it cannot only perform the power transfer during an entire switching period but also achieve the high power factor due to the flyback operation. Moreover, since the current balanced capacitor can minimize the offset current through the transformer magnetizing inductor regardless of the AC input voltage, the core loss and volume of the transformer can be minimized. Therefore, the proposed converter features a high efficiency and high power factor. To confirm the validity of the proposed converter, theoretical analysis and experimental results from a prototype of 24W LED driver are presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.671-680
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• 2005

The CFL linearisation chip which is one of key devices in ultra-narrowband mobile radio transmitter using CQPSK digital modulation method is designed and implemented with $0.35{\mu}m$ CMOS technology. The reduced size and low cost of transmitter are available by the use of direct-conversion and CFL ASIC chip, which improve the power effi챠ency and linearity of transmitting path. In addition, low power operation is possible through CMOS technology The performance test results of transmitter show -25 dBc improvement of IMD level at the 3 kHz frequency offset and then satisfy FCC 47 CFR 90.210 E emission mask in the operation of CFL ASIC chip. At that time, the transmitting power is about PEP(Peak-to-Envelope Power) 5 W. The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.