I. INTRODUCTION
Due to the rapid growth of electricity consumption and large-scale utilization of renewable energy, multilevel converters are playing increasingly important roles in industrial applications due to their advantages in terms of high efficiency, low EMI noise, good harmonic features, and the ability to withstanding high voltage via low-voltage devices [1]-[10]. In 2000, a generalized multilevel converter was proposed, as shown in Fig. 1(a), which presented a generalized concept for multilevel converters [5]. Many of the existing multilevel converters (e.g., the well-known neutral-point clamped converter (NPC) and the flying-capacitor (FC) converter) were derived from this topology [6]-[10].
Fig. 1.Relationship of three multilevel converters: (a) Generalized multilevel converter, (b) Traditional MMC, and (c)New MMC.
Another recently introduced multilevel converter called the modular multilevel converter (MMC) is depicted in Fig. 1(b), which is cascaded by a series of half-bridge sub-modules (SMs). Compared with other multilevel converters, the MMC shows higher modularity and scalability and can be applied to very high-voltage applications (i.e. HVDC) [11], [12].
In addition, in [9] and [10], a new multilevel topology (see Fig. 1(c) was proposed by conserving the shadowed devices in Fig. 1(a). This topology was referred to as a new MMC (N-MMC) by the authors, and the only difference between it and the traditional MMC is the introduction of a middle SM. As a result, compared with the traditional MMC, the N-MMC is able to save one SM per phase while providing the same output voltage. However, due to the employment of the middle SM, the symmetry between the upper-arm and lower-arm SMs is no longer satisfied. The modulation schemes and capacitor voltage balancing methods used in the traditional MMC [11]-[20] are not applicable to the N-MMC. In [9] and [10], a phase-disposition carrier PWM (PD-PWM) as well as a voltage balancing method based on a sorting algorithm were proposed.
However, it has to be admitted that there are still some flaws:
Therefore, this paper proposes a novel phase-shifted carrier (PSC) modulation scheme for the N-MMC, with the advantages of optimized harmonic features and evenly distributed switching frequency and power losses. Moreover, a novel capacitor voltage balancing control scheme is further presented for the PSC-PWM, in which the unwanted dc offset current can be avoided. In addition, the complexity of the control system can be reduced since the centralized sorting calculation is replaced by a series of individual proportional controllers.
The rest of this paper is organized as follows. The mathematical model of the N-MMC is reviewed in Section II. A PSC modulation scheme for the N-MMC is presented in Section III. Section IV explains the proposed capacitor voltage balancing scheme. Experimental results conducted on a downscaled prototype are included in Section V. Finally, Section VI concludes this paper.
II. BASIC OPERATING PRINCIPLES OF THE N-MMC
A. Topology Description
The circuit configuration of a three-phase N-MMC is shown in Fig. 2. Each of its phases comprises 2N+1 identical SMs: N upper-arm SMs, N lower-arm SMs, and one middle SM, which are connected through two buffer inductors L. Each SM contains a capacitor and two insulated-gate bipolar transistors (IGBT) S1 and S2. Consequently, each SM has two working states: the ON-state, when S1 is switched on and S2 is switched off; and the OFF-state, when S2 is switched on and S1 is switched off.
Fig. 2.Circuit configuration of the new MMC (N-MMC).
B. Mathematical Model
A circuit diagram of phase A of the N-MMC is shown in Fig. 2. It is similar to phase B and phase C. uoj is the output voltage of phase j (j∈{A, B, C}), ioj is the phase current, and E is the dc-link voltage. uuj(i) and uwj(i) (i∈{1, 2, … N}) represent the output voltage of the i-th SM in the upper arm or the lower arm, respectively. uuj, iuj and uwj, iwj represent the voltages and currents of the upper arm and the lower arm, respectively. Note that a single coupled inductor is used for the analysis in Fig. 2, in which no equivalent inductor appears at the ac terminal compared to the case of two separate inductors [19]. As a result, the actual output voltage can be accurately derived in default of the voltage drop across the equivalent inductor. In each SM, the capacitor voltages of the upper-arm SMs and lower-arm SMs are equal to Uc. However, when the capacitor voltage of the middle SM is Ucm, there is a constraint as follows:
Then the following equations can be obtained by Kirchhoff’s voltage law:
where L is the self-inductance, and M is the mutual inductance between the upper-arm SMs and the lower-arm SMs (M=L).
Hence, the expressions (1)–(3) can be derived as:
In addition, icirj is defined as the circulating current, which circulates through both the upper and lower arms and can be given by:
Ideally, the phase current ioj would be split equally between these two arms, and the arm currents can be expressed as:
Moreover, by combining expressions (2) and (5), the dc-loop dynamic equation can be obtained as:
III. PROPOSED PSC MODULATION FOR THE N-MMC
The modulation schemes used in traditional MMC are not applicable any more due to the asymmetric structure of the N-MMC. Therefore, the proposed PSC-PWM with an optimal phase-shifted angle will be analyzed in this section. In addition, in order to suppress the harmonics of the phase voltage, the situation will be further discussed when the middle SM capacitor voltage employs 0.5Uc and Uc, respectively.
A. Description of the Proposed PSC Modulation for the N-MMC
The proposed PSC modulation scheme for the N-MMC with N SMs per arm is illustrated in Fig. 3. There are a total of 2N+1 triangular carriers with a frequency of fc (Cm for the middle SM, Cu1–CuN for the SMs in the upper arm, and Cw1–CwN for the SMs in the lower arm). Each SM is assigned with a particular triangular carrier, so that all of the SMs have the same switching frequency and the semiconductor stresses are evenly distributed. Moreover, the triangular carriers are phase-shifted with respect to each other by the phase-shift angle:
Fig. 3.Phase-shifted Carrier pulse width modulation (PSC-PWM) for the N-MMC.
By choosing the phase angle of the middle SM as
the phase angle of the i-th (i=1, 2…N) carrier Cui in the upper arm can be obtained as:
As for the i-thcarrier Cwi in the lower arm, it is:
On the other hand, the reference signal is expressed as:
where M (0 ≤ M ≤ 1) denotes the modulation ratio, ωo is the angular frequency of the output ac voltage, and φ is the phase angle. Then, the switching pulses of each of the SMs are generated by comparing the reference signal with the corresponding carrier wave. For the middle SM and the lower-arm SMs, it is in the ON-state when the reference is greater than the carrier, and it is in the OFF-state when the carrier is greater than the reference. In contrast, with respect to the upper-arm SMs, the SM will be in the OFF-state when the reference is higher while it is in the ON-state when the carrier is higher.
Based on a Fourier series analysis [22], the Fourier representation of the output voltage of the middle SM, the upper-arm SMs, and the lower-arm SMs can be expressed as:
where ωc is the angular frequency of the triangular carriers, m is the harmonic order of the carrier wave, n is the harmonic order of the reference wave, and Jn(x) refers to the Bessel function of the order n and the argument x.
B. Harmonics of the Output Voltage when Ucm=0.5Uc
When the capacitor voltage of the middle SM is set as 0.5UC, substitution of (13) into (4) leads to:
where according to (1), Uc can be derived as:
Furthermore, since:
all of the switching harmonics of uoj will be eliminated except those at 2N+1 multiples of the carrier frequency and their sideband components, that is:
Equation (17) indicates that with the switching frequency of fc to each of the SMs, the equivalent switching frequency of the output voltage of the N-MMC can increase to (2N+1)fc, leading to a significant reduction in the filter size.
Although the best harmonic features can be achieved when Ucm is selected as half of Uc, the drawback is that the output voltage capability of the middle SM is not fully utilized. Therefore, this case is applicable when the dc-link voltage E is lower than the rated value.
C. Harmonics of the Output Voltage when Ucm=Uc
Alternatively, in order to assure full utilization of the middle SM, its capacitor voltage is set equal to Uc. Therefore:
Similarly, the output voltage can be expressed by the Fourier series as (19). Compared to (17), it can be seen that the output voltage in this case contains more harmonic components because the harmonics of the middle SM cannot be completely cancelled out. As a result, harmonics around the fc frequency and its multiples will appear. Nonetheless, the amplitude of these newly introduced harmonics is relatively small and acceptable, which will only cause a slight deterioration in the output current waveform. This will be confirmed by the simulation and experimental results.
D. Simulation Results
Figs. 4 and 5 show the simulated waveforms of the N-MMC with two SMs per arm. The simulated parameters include, the fundamental frequency f=50Hz, modulation ratio M=0.95, buffer inductor L=2.5mH, rated capacitor voltage Uc=100V, carrier frequency fc=1kHz, and the loads of Rload=3000Ω, Lload=3mH. Specifically, to ensure the harmonic features of the proposed PSC-PWM scheme not affected by other factors (such as the capacitor voltage ripple and the capacitor voltage unbalance), an infinite capacitance for each of the SMs is assumed here.
Fig. 4.Simulation waveforms for the output voltage of phase A and its harmonic spectrum when Ucm=Uc.
Fig. 5.Simulation waveforms for the output voltage of phase A and its harmonic spectrum when Ucm=0.5Uc.
Fig. 4 depicts the output voltage of phase A and its harmonic spectrums when Ucm=Uc, where the number of voltage levels is seven. In addition, the FFT results show that the voltage harmonics mainly concentrate on frequencies of 1kHz (=fc) and 5kHz (=5fc). On the other hand, with respect to Ucm=0.5Uc, the simulation results are shown in Fig. 5. Although the output voltage contains only six voltage levels, it should be noted that the voltage waveform is much smoother (without spikes) than that in Fig. 4, and that the harmonic spectrums in this case are mainly around 5kHz (=5fc), leading to better harmonic features. All of these simulation results are in good agreement with the above analyses of the proposed PSC modulation scheme.
IV. PROPOSED CAPACITOR VOLTAGE BALANCING CONTROL FOR THE N-MMC
SM capacitor voltage balancing control for the traditional MMC has been widely discussed in the literature [17]-[21]. With respect to the N-MMC, these existing methods are not applicable due to the existence of the middle SM. Reference [10] regulates the capacitor voltage of the middle SM Ucm by judging the sign of the output current ioj. When ioj is positive and Ucm is overly high, the middle SM will be inserted for a longer time to discharge itself. On the other hand, when ioj is positive and Ucm is overly low, the middle SM will be bypassed for a longer time to charge itself. Consequently, the dc offset of the output current ioj will be introduced because the balancing method distorts the sinusoidal output of the middle SM, leading to a dc offset current at ioj.
In order to solve this problem, a novel voltage balancing control scheme is proposed, as shown in Fig. 6. It comprises two controllers: a phase energy balancing controller for the energy stability of each phase; and a SM balancing control for the voltage regulation of each SM capacitor. The phase energy balancing controller forces (N+1)Uavg_j to follow the dc-bus voltage E, where Uavg_j is the average capacitor voltage of the 2N+1 SMs within phase j. This process is accomplished by adjusting the inner-loop circulating current icirj. It should be noted that since the circulating current directly flows through the capacitor of the middle SM and the dc-bus, the term of “E-Ucm” is used as a feed-forward compensation at the output of the PI controller.
Fig. 6.Block diagram of the proposed balancing scheme: (a) Phase energy balancing control and (b) SM balancing control.
With respect to the SM balancing controller, it is ensured that the capacitor voltage of each of the SMs is equal to a desired voltage Uc_ref by adjusting its terminal voltage based on the amplitude of the output current ioj rather than the sign of ioj to avoid the introduction of a dc offset. Note that with regard to the upper-arm and lower-arm SMs, Uc_ref is always set as Uavg_j.. Meanwhile, value of Uc_ref for the middle SM can be chosen as either Uavg_j or 0.5 Uavg_j depending on the settings of the PSC-PWM. Fig. 7 shows the complete implementation of the proposed balancing control scheme combined with the aforementioned PSC-PWM. The sum of the outputs of the phase energy balancing controller u*Pj and the SM balancing controller u*SMj(i) are used as voltage adjustments attached to the sinusoidal reference signal in the PSC-PWM.
Fig. 7.Implementation of the balancing control scheme under the proposed PSC-PWM.
V. EXPERIMENTAL RESULTS
A. System Configuration
A downscale three-phase N-MMC prototype is built to verify the effectiveness of the proposed modulation and balancing schemes. The system configuration is shown in Fig. 8, where the N-MMC is operated as an inverter and the dc-bus voltage is obtained by using a three-phase diode rectifier. As shown in Fig. 9, each arm employs two SMs. In other words, there are a total of five SMs per phase. The circuit parameters of the prototype are summarized in Table I.
Fig. 8.System configuration used for experiment..
Fig. 9.Photograph of the laboratory setup.
TABLE ILABORATORY PROTOTYPE SPECIFICATIONS
Fig. 10 shows the control system used for the experiment. The architecture of a digital signal processor (DSP) plus a field-programmable gate array (FPGA) is adopted as the central controller, where a TMS320F28335 DSP is used to generate the three-phase sinusoidal references while an EP3C25Q240C8 FPGA is adopted to generate the triangular carriers with a phase-shift angle of 72° (=360°/5, as illustrated in Fig. 2). Each of the SMs is controlled by an EPM570T100 complex programmable logic device (CPLD), which receives PWM signals via optical fibers and sends back monitored capacitor voltages. Furthermore, all of the experimental waveforms are acquired through a DL850 scopecorder.
Fig. 10.Controller architecture used for experiment.
B. Operating Performance when the Middle SM Capacitor Voltage is Ucm=Uc
Fig. 11 presents experimental results when the middle SM capacitor voltage Ucm is set as 100V and the dc-bus voltage is E=300V. In the steady state, Fig. 11(a) shows the sinusoidal phase current of ioA and the five SM capacitor voltages. It is seen that all five of the capacitor voltages coincide with each other around 100V, which verifies the validity of the proposed capacitor voltage balancing scheme. Fig. 11(b) shows the phase voltage uoA. The number of voltage levels of the uoA phase is seven. However, it seems to be blurring due to the existence of voltage spikes. Further, as depicted in Fig. 11(c), the harmonics of uoA are located at the frequencies of multiples of 3kHz (=fc), which confirms the PSC-PWM scheme as analyzed in (17).
Fig. 11.Experimental waveforms when middle SM capacitor voltage Ucm =Uc: (a) Phase current and capacitor voltages under steady state, (b) Phase voltage under steady state, (c) Harmonic spectrum of the phase voltage, and (d) Capacitor voltages under transient state.
Moreover, Fig. 11(d) exhibits the transient-state performance of the proposed capacitor voltage balancing scheme. Firstly, the balancing scheme was intentionally disabled, and it is observed that the capacitor voltages gradually disperse. Then, after re-enabling the SM balancing control scheme, the capacitor voltages quickly converged and they were finally balanced again.
C. Operating Performance when the Middle SM Capacitor Voltage is Ucm=0.5Uc
When the middle SM capacitor voltage Ucm is set as half of Uc (i.e., 50V) and the dc-bus voltage is E=250V, the corresponding experimental results are illustrated in Fig. 12. The steady-state waveforms are shown in Figs. 12(a) and 12(b), while the transient-state waveform is exhibited in Fig. 12(d). In the steady state, the phase current ioA and the SM capacitor voltages are presented in Fig 12(a). With the proposed capacitor voltage balancing scheme, both the upper-arm and lower-arm SM capacitor voltages are around 100V, while the middle SM capacitor is well maintained at 50V. Fig. 12(b) shows the phase voltage uoA. The number of voltage levels of uoA in this case is six, which is less than the waveform in Fig. 11(b). Nonetheless, uoA here is much smoother than that shown in Fig. 11(b). Fig. 12(c) shows the harmonic spectrum of uoA. Compared with Fig. 11(c), it is clear that the magnitudes of all of the harmonics are reduced except for the frequencies around 15kHz (=5fc). Note that the harmonics below 5fc are not eliminated as desired. This is due to the fact that the voltage balancing control inevitably alters the references of each of the SMs and impairs the results of the PSC modulation. Regardless, the effectiveness of the PSC-PWM can still be demonstrated.
Fig. 12.Experimental waveforms when middle SM capacitor voltage Ucm=0.5Uc: (a) Phase current and capacitor voltages under steady state, (b) Phase voltage under steady state, (c) Harmonic spectrum of the phase voltage, and (d) Capacitors voltages under transient state.
Moreover, the transient-state experimental waveforms are shown in Fig. 12(d), where the SM balancing control was disabled and then re-enabled. This also indicates the good performance of the proposed balancing control scheme.
VI. FURTHER SIMULATION RESULTS OF THE N-MMC IN GRID-CONNECTED APPLICATIONS
Since one of the most promising applications of multilevel converters is use as a grid-connected converter, a further study of the performance of the N-MMC as a three-phase grid-connected rectifier is provided in this Section. The study is based on a simulation in the MATLAB/Simulink environment, with five SMs per arm. That is, there are a total of eleven SMs per phase, and the capacitor voltage of the middle SM is selected as Ucm=Uc. The system configuration for the simulation is shown in Fig. 13. Detailed parameters of the simulated circuit and the operating conditions are listed in Table II. It should be noted that since the ac terminals of the N-MMC are clamped by the grid voltages, the harmonic features of the output voltages cannot be tested in this case. Thus, only the control performances are verified.
Fig. 13.System configuration used for simulation.
TABLE IISIMULATION SPECIFICATIONS
Fig. 14 presents the simulation waveforms. It can be seen that the output dc voltage udc is well regulated at 5kV, and that the absorbed active power from the grid is 500kW. Initially, no reactive power is required by the N-MMC. Therefore, the input currents are in phase with the grid voltages showing a unity power factor. After t=100ms, the 300kVar reactive power is commanded to be sent to the grid. During both the steady states and the dynamic states, the output dc voltage is stable and the input ac currents are well controlled. Moreover, the capacitor voltages are kept well balanced. It can be concluded that the N-MMC is a good candidate for grid-connected applications.
Fig. 14.Simulation results: (a) output dc voltage udc, (b) three-phase grid voltages, (c) three-phase input currents, (d) active power and reactive power, (e) five upper-arm SM capacitor voltages of phase-A, (f) five lower-arm SM capacitor voltages of phase-A, and (g) middle-SM capacitor voltage of phase-A.
VII. CONCLUSION
In this paper, PSC modulation and balancing schemes have been proposed for the N-MMC. The harmonic features of the output voltage are also investigated by Fourier analysis. With the proposed PSC modulation, each of the SMs has the same switching frequency and the semiconductor stresses are evenly distributed. In addition, when the middle SM capacitor voltage employs half of the other capacitor voltage, the harmonics of the output voltage are better than when employing the same voltage with other capacitors. Nonetheless, the amplitude of these newly introduced harmonics is still relatively small and acceptable whether the middle SM adopts half or one of the other capacitor voltage. Furthermore, the balancing control is realized by adjusting the amplitude of the reference signal rather than the offset in order to avoid introducing a dc component in phase current.
Moreover, a three-phase N-MMC prototype was built and tested in the laboratory. Experimental results confirm the validity of the proposed PSC modulation and balancing strategy and show very good static and dynamic performances. Finally, a simulation study is provided to show the effectiveness of the N-MMC as a grid-connected converter.
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