• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.28 no.1
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• pp.39-44
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• 1992

Analog PID controllers have been designed to make good use of position control in industries. Recently, the importance of digital position control is emphasized for the requirements of controller which are not only to control the objects but to include various aspects such as easiness of design and implementation, simple exchange of control program and convenient communications of data between various controllers and a host computer. This study proposes a combined control method which is mixed the vaiable structure control (VSC) with the PI control for minimum time position control of DC servo motor by microcomputer. The results of test by this method show offset-free and minimum time optimal position control which is not affected by the disturbance and the system parameter variations. The validity of the proposed method comparing with the conventional PID control is proved by the response experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.538-548
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• 2014

This study provides a robust control of a grid-connected three-phase two-level photo voltaic inverter. The introduced control method uses the cascade control strategy to regulate AC-side current and DC-link voltage. A robust controller with integration action is used for the inner-loop AC-side current control, which maximizes the convergence rate using a linear matrix inequality-based optimization design method and eliminates the offset error. The robust controller design method considers the parameter uncertainty set to accommodate parameter mismatch and un-modeled components in the inverter model. An outer-loop proportional-integral controller is used to regulate DC-link voltage with linearization of DC/AC relation. The proposed control strategy is applied to a grid-connected 100 kW photo voltaic inverter.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.510-511
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• 2013

3상 인버터 출력단 센싱에 옵셋이 발생할 경우 DC 전류에 출력 주파수에 해당하는 리플 성분이 발생하게 된다. 리플의 크기는 옵셋의 크기에 비례하여 커지게 된다. 센싱 단자 등의 H/W적인 문제로 옵셋이 발생할 경우 DQ축 전류 및 DC 전류에 리플이 발생하게 되고 이는 필터 리액터, 변압기 등의 온도 상승 및 IGBT Stack의 온도 상승 등 인버터 시스템에 악영향을 유발시킬 뿐만 아니라 DC 소스원에도 악영향을 발생시킬 가능성이 존재한다. 따라서, 본 논문에서는 옵셋의 영향을 줄여 시스템을 안정적으로 동작시키기 위해 옵셋 보상 방법을 제안하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.369-372
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• 2017

This paper presents a control scheme for three-level NPC inverters using small DC-link capacitors. To reduce the inverter system volume, the film capacitor with small capacitance is a promising candidate for the DC-link. When small capacitors are applied in a three level inverter, however, the AC ripple component increases in the DC-link NPV (neutral point voltage). In addition, the three-phase input grid currents are distorted when the DC-link capacitors are fed by diode rectifier. In this paper, the additional circuit is applied to compensate for small capacitor systems defect, and the offset voltage injection method is presented for the stabilization in NPV. These two proposed processes evidently ensure the quality improvement of the input grid currents and output load currents. The feasibility of the proposed method is verified by experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.735-742
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• 2006

In this paper, we explain the operation scheme and fixed-point design method of DFE (Digital Front End), which performs DC offset compensation, automatic frequency control, and automatic gain control over the input signal to the UE (User Equipment) receiver of IEEE 802.16e OFDMA-TDD system. Then, we analyze the performance of DFE under ITU-R M. 1225 Veh-A 60km/h channel environment. To optimize the fixed-point design of DFE, we reduce the number of bit resulted from calculation without performance degradation, leading to the decreased complexity of the operation in H/W, and design the Loop filter with considering trade-off between the Acquisition time and the Stability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.23-29
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• 2011

A dB-linearity improved variable gain amplifier (VGA) for GPS receiver is presented. The Proposed dB-linear current generator has improved dB-linearity error of ${\pm}0.15$dB. The VGA for GPS is designed using proposed dB-linear current generator and composed of 3 stage amplifiers. The IF frequency is assumed as 4MHz and the linearity requirement of the VGA for GPS receiver is defined as 24dBm of IIP3 using cascaded IIP3 equation and the VGA satisfies 24dBm when minimum gain mode. The DC-offset voltage is eliminated using DC-offset cancelation loop. The gain range is from -8dB to 52dB and the dB-linearity error satisfies ${\pm}0.2$dB. The 3-dB frequency has range of 35MHz~106MHz for the gain range. The VGA is designed using 0.18${\mu}m$ CMOS process. The power consumption is 3mW with 1.8V supply voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.318-325
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• 2008

A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a $0.13\;{\mu}m$ CMOS process. A digital calibration of DC reference voltage is proposed for the $1^{st}$ preamp array to compensate for the input offset voltage of differrential amplifiers without disturbing the high-speed signal path. A 3-stage cascaded voting process is used in the digital encoder block to eliminate the conescutive bubbles up to seven completely, if the $2^{nd}$ preamp output is assumed to have a single bubble at most. ENOB and the power consumption were measured to be 5.88 bits and 212 mW with a 195 MHz $400\;mV_{p-p}$ sine wave input.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2395-2402
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• 2013

An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are $450{\times}210{\mu}m^2$ and 6.71mW.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.184-186
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• 2005

The effect of power supply noise on the phase noise of a ring oscillator is studied. The power supply noise source in series with DC power supply voltage is applied to a 3 stage CMOS ring oscillator. The phase noise due to the power supply noise is modeled by the narrow band phase modulation. The model is verified by the fact that the spectrum of output of ring oscillator has two side bands at the frequencies offset from the frequency of the ring oscillator by the frequency of the power supply noise source. Simulations at several different frequency of the power supply noise reveals that the ring oscillator acts as a low pass filter to the power supply noise. This study, as a result, shows that the phase noise generated by the power supply noise is inversely proportional to the frequency offset from the carrier frequency.