• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.249-252
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• 2000

A new Smart rower IC's based on the Partial SOI technology was designed for such applications as mobile communication systems, high-speed HDD systems etc. A new methodology of integrating a 0.8${\mu}{\textrm}{m}$ BiCMOS compatible Smart Power technology, high voltage bipolar device, high speed SAVEN bipolar device, LDD NMOSFET and a new LDMOSFET based on the Partial SOI technology is presented in this paper. The high voltage bipolar device has a breakdown voltage of 40V for the output stage of analog circuit. The optimized Partial SOI LDMOSFET has an off-state breakdown voltage of 75 V and a specific on- resistance of 0.249mΩ.$\textrm{cm}^2$ with the drift region length of 3.5${\mu}{\textrm}{m}$. The high-speed SAVEN bipolar device shows cut-off frequency of about 21㎓. The simulator DIOS and DESSIS has been used to get these results.

• Transactions on Electrical and Electronic Materials
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• v.7 no.5
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• pp.224-229
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• 2006

Many studies have been done on the application of residual charge measurement in cable degradation diagnosis. In this paper, the behavior of residual charges measured with water-tree degraded XLPE sheets and cable are discussed. At charge injection process, the charge is injected by applying dc voltage as a conventional method, suddenly cut-off ac voltage or impulse voltage. Therefore the residual charge is influenced by the applying process. At charge release process, transient dc current flows when applying ac high voltage and also ac high voltage superimposed to dc low voltage. From the results, new diagnosis method is suggested.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.239-242
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• 1999

In this paper, we report the process/device design of high-speed, high-voltage SOI smart power IC for mobile communication system, high-speed HDD system and the electronic control system of automobiles. The high voltage LDMOS with 70V breakdown voltage under 0.8${\mu}{\textrm}{m}$ design rule, the high voltage bipolar with 40V breakdown voltage for analog signal processing, the high speed bipolar with cut-off frequency over 20㎓ and LDD NMOS for high density were proposed and simulated on a single chip by the simulator DIOS and DESSIS. And we extracted the process/device parameters of the simulated devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.104-113
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• 1994

We have fabricated n-p-n HBTs using 3-inchAlgaAs/GaAs hetero structure epi-wafers grown by MBE. DC and AC characteristics of HBT devices were measured and analyzed. For HBT epi-structure, Al composition of emitter was graded in the region between emitter cap and emitter. And base layer was designed with concentration of 1${\times}10^{19}/cm^{3}$ and thickness of 50nm, and Be was used as the p-type dopant. Principal processes for device fabrication consist of photolithography using i-line stepper, wet mesa etching, and lift-off of each ohmic metal. The PECVD SiN film was used as the inslator for the metal interconnection. HBT device with emitter size of 3${\times}10{\mu}m^{2}$ resulted in cut-off frequency of 35GHz, maximum oscillation frequency of 21GHz, and current gain of 60. The distribution of the ideality factor of collector and base current was very uniform, and the average values of off-set voltage and current was very uniform, and the average values of off-set voltage and current gain were 0.32V and 32 within a 3-inch wafer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.11
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• pp.1925-1929
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• 2007

This paper is studied on a novel Electric Safety Protection Device (ESPD) of high speed for incapable operation of Earth Leakage Circuit Breaker (ELB) and Molded_case Circuit Breaker (MCCB) using the low voltage distribution line. The major causes of electrical fire are classified to short circuit fault, overload fault, electric leakage and electric contact failure. The occurrence factor of the fire is electric arc or spark accompanied with electrical faults. Residual Current Protective Device (RCD), that is ELB and MCCB, of high sensitivity type used at low voltage wiring cuts off earth leakage and overload, but the RCD can't cut off electric arc or spark to be a major factor of electrical fire. As the RCDs which are applied low voltage distribution panel are prescribed to rated breaking time about 30[ms] (KS C 4613), the RCDs can't perceive to the periodic electric arc or spark of more short wavelength level. To be improved on such problem, this research development is proposed to a novel ESPD of high speed to trip of distribution line on electric arc or spark due to electrical fire. Some experimental results of the proposed ESPD are confirmed to the validity of the analytical results.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.1
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• pp.39-45
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• 2012

Currently, the aircraft industry, aircraft parts as well as airframe have been developed in producing, the aircraft parts and fuselages have been produced the product by cutting rather than forging and casting because of the residual stress and stress concentration. In this study, the aircraft is being used in many parts of aluminium alloy 2024 in wire-cut E.D.M. The selected experimental parameters are peak current, no-load voltage, off time and feed rate. It is found that cutting mountain part on surface roughness of the curve 0.3mm than 0.25mm diameter wire electrode is stable in many uniform distribution.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.04a
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• pp.14-18
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• 1996

From the experimental study of Wire-Cut EDM of die-material(SKD-11), machining characteristics such as machining rate, surface roughness and hardness have been observed and evaluated under the conditions varing pulse on time, pulse off time, peak voltage after fixing other conditions. It was found that various operating conditions have significant influences on machining rate, surface roughness. Hardness of workpiece was unaffected by operating conditions.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.5
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• pp.101-106
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• 2008

In the wire cut electrical discharge machining, the optimal machining parameters setting satisfying the requirements of both high efficiency and good quality is very difficult because its process involves a series of complex physical phenomena and the machining parameters are numerous over diverse range. In this paper, the experimental investigation has been performed to find out the influence of the machining parameters on the machining performance such as cutting speed and surface roughness. The selected experimental parameters are no load voltage, discharge peak current and pulse-off time. The experimental results give the guideline for selecting suitable machining parameters.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.21-25
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• 2006

This paper describes the novel control techniques design of VSC(Voltage Sag Corrector) for the purpose of power line quality enhancement. A fast detecting technique of voltage sag is implemented through the detection of instantaneous value on synchronous rotating do-reference frame. The first order digital filter is added in the detection algorithm to protect the insensitive characteristics against the noise. The relationship between the total detection time and cut-off frequency of the filter is described. The size of the capacitor bank used as the energy storage element is designed from the point of view of input/output energy with circuit analysis. Finally, the validity of the proposed scheme is proven through the simulated results.