• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.147-156
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• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• Journal of Power Electronics
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• v.16 no.3
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• pp.840-848
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• 2016

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.278-281
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• 1988

This paper realizes the multi-output truncated difference circuits using current mode CMOS, and presents the algorithm designing multi - valued logic functions of a given multivalued truth tables. This algorithm divides the discrete valued functions and the interval functions, and transforms them into the truncated difference functions. The transformed functions are realized by current mode CMOS. The technique presented here is applied to MOD4 addition circuit and GF(4) multiplication circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.76-82
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• 2002

This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.72-79
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• 2003

This paper proposes a 32${\times}$32 Modified Booth multiplier using CMOS multiple-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 67.1% and 37.3%, compared with that of the voltage mode binary multiplier and the previous multiple-valued logic multiplier, respectively. The multiplier is designed with a 0.35${\mu}{\textrm}{m}$ standard CMOS technology at a 3.3V supply voltage and unit current 10$mutextrm{A}$, and verified by HSPICE. The multiplier has 5.9㎱ of propagation delay time and 16.9mW of power dissipation. The performance is comparable to that of the fastest binary multiplier reported.