• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.4
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• pp.224-230
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• 2006

The conventional way to implement a bidirectional converter with boost/buck has been to use two general purpose PWM ICs with a single supply voltage. In this case, when one direction mode is in operation, the other is disabled and the output of the error amplifier of the disabled IC may be saturated to a maximum value or zero. Therefore, during mode transition, a circuit which can disable the switching operation for a certain time interval is required making it impossible to get a seamless transition. In this paper, the limitations of the conventional 42V/14V bi-directional DC/DC converter implemented with general current mode PWM ICs with a single supply voltage are reviewed and a new current mode PWM controller circuit with a dual voltage system is proposed. The validity of the proposed circuit is investigated through simulation. and experiments.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.207-214
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• 2019

In this study, discrete-time domain analysis is proposed to investigate the input current of a buck AC/DC light-emitting diode (LED) driver. The buck power factor correction converter can operate in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). Two discontinuous and two continuous conduction operating modes are possible depending on which event terminates the conduction of the main switch in a switching cycle. All four operating modes are considered in the discrete-time domain analysis. The peak current-mode control with slope compensation is used to design a low-cost AC/DC LED driver. A slope compensation design of the buck AC/DC LED driver is described on the basis of a discrete-time domain analysis. Experimental results are presented to confirm the usefulness of the proposed analysis.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.2
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• pp.97-104
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• 2017

In the present industrial field, the demand for the development of the solar power source device and the charging device for the solar cell is gradually increasing. The solar charger is largely divided into a DC-DC converter that converts the voltage generated from the sunlight to a charging voltage, and a battery and a charger that are charged with an actual battery. The conventional charger topology is used either as a Buck converter or a Boost converter alone, which has the disadvantage that the battery can not always be charged to the desired maximum power as input and output conditions change. Although studies using a topology capable of boosting and stepping have been carried out, Buck-Boost converters or Sepic converters with relatively low efficiency have been used. In this paper, we propose a new Buck Boost combination power converter topology structure that can use Buck converter and Boost converter at the same time to improve inductor current ripple and power converter efficiency caused by wide voltage control range like solar charger.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.864-870
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• 2017

This paper describes a Dual Buck Converter with mode control using variable Frequency to Voltage for portable devices requiring wide load current. The inherent problems of PLL compensation and efficiency degradation in light load current that the conventional hysteretic buck converter has faced have been resolved by using the proposed Dual buck converter which include improved PFM Mode not to require compensation. The proposed mode controller can also improve the difficulty of detecting the load change of the mode controller, which is the main circuit of the conventional dual mode buck converter, and the slow mode switching speed. the proposed mode controller has mode switching time of at least 1.5us. The proposed DC-DC buck converter was implemented by using $0.18{\mu}m$ CMOS process and die size was $1.38mm{\times}1.37mm$. The post simulation results with inductor and capacitor including parasitic elements showed that the proposed circuit received the input of 2.7~3.3V and generated output of 1.2V with the output ripple voltage had the PFM mode of 65mV and 16mV at the fixed switching frequency of 2MHz in hysteretic mode under load currents of 1~500mA. The maximum efficiency of the proposed dual-mode buck converter is 95% at 80mA and is more than 85% efficient under load currents of 1~500mA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• Journal of Power Electronics
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• v.18 no.3
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• pp.879-891
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• 2018

A bidirectional dc-dc converter is used in battery energy storage systems owing to the growing requirements of a charging and discharging mode of battery. The magnetic coupling of output or input inductors in parallel-connected multi modules of a bidirectional dc-dc converter is often utilized to reduce the peak-to-peak ripple size of the inductor current. This study proposes a novel design guideline to achieve minimal ripple size of the inductor current under bidirectional power flow. The newly proposed design guideline of optimized coupling factor is applicable to the buck and boost operation modes of a bidirectional dc-dc converter. Therefore, the coupling factor value of the coupled inductor does not have to be optimized separately for buck and boost operation modes. This new observation is explained using the theoretical model of coupled inductor and confirmed through simulation and experimental test.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.19-26
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• 2016

In this study, a bidirectional DC-DC converter for idle stop and go (ISG) is developed to reduce fuel consumption. A three-phase non-isolated half-bridge converter is selected through a design method by considering efficiency and volume. According to the state of charge of the batteries at both the low-voltage and high-voltage sides, buck mode, which charges a low-voltage battery from the generated motor energy, and boost mode, which provides power to the motor from the low- and high-voltage battery sides, are required in the ISG system. Hence, an autonomous and seamless bidirectional control method using a variable current limiter is proposed for mode change. A 1.8 kW engineering sample of the proposed converter has been built and tested to verify the validity of the proposed concept. The maximum efficiencies, including gate driver and control circuit losses, are 96.4% in charging mode and 96.1% in discharging mode.

• Proceedings of the KIPE Conference
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• 1998.11a
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• pp.44-48
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• 1998

In the buck-boost DC-DC converter which is used at a certain situation such as in factories where loads often change a lot, the switches in the device make big energy loss in operating at Buck-Boost Mode due to hard switching and are affected by lots of stresses which decrease the efficiency rate of the converter. In order to improve this problem, to decrease the loss of snubber and switching, it has been investigated that zero voltage switching mode and zero current switching mode which make the operation of switches with soft switching. For the more sophisticated and advanced device, this paper is presented the Partial Resonant Soft Switching Mode Power Converter which is adapted the power converter having the partial resonant soft switching mode, that makes switches operate when the resonant current or voltage becomes zero by making the resonant circuit partially at turning on and off of the switches with suitable layout of the resonant elements and switch elements in the converter. Also, this paper includes the analysis and simulation of the Partial Resonant type Buck-Boost Chopper.