• Title/Summary/Keyword: Current-gain cutoff frequency

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Current Gain Characteristics of AlGaAs/GaAs HBTs with different Temperatures (온도변화에 따른 AlGaAs/GaAs HBT의 전류이득 특성)

  • 김종규;안형근;한득영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.840-843
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    • 2001
  • In this study, temperature dependency of current gain for AlGaAs/GaAs/GaAs HBT is analytically proposed over the temperature range between 300K and 600K. Energy bandgap, effective mass, intrinsic carrier concentration are considered as temperature dependent parameters. Collector current which is numerically calculated is then analytically expressed to enhance the speed of calculation for current gain. From the results, current gain decreases as the temperature increases. These results will be used to expect the unity current gain frequency f$_{T}$ in conjunction with emitter-base and collector- base capacitances.s.

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Design of an AlGaAs/GaAs Double-Heterojunction Power FET (AlGaAs/GaAs double-heterojunction 전력용 FET의 설계)

  • 박인식;김상명;신석현;이진구;신재호;김도현
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.8
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    • pp.57-62
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    • 1993
  • In this paper, both feasible power gain and power added efficiency at the operating center frequency of 12 GHz are stressed to design a power FET with double-heterjunction structure. The variable parameters or the design are the unit gate width, the gate length, the doping density of AlGaAs, the AlGaAs thickness, the spacer thickness, the Al mole fraction, and the GaAs well thickness. The results of simulation for the FET with 1.mu.m gate length show that the power gain and the power added efficiency are 10.2 dB and 36.3% at 12GHz, respectively. An extrapolation of the relation between current gain and unilateral gain yields a 17 GHz cutoff frequency and 43GHz maximum frequency of oscillation. The calculation of the current versus voltage characteristics show that the output power of the device is about 0.62W.

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Design of a Current-Mode Analog Filter for WCDMA Baseband Block (WCDMA 베이스밴드단 전류모드 아날로그 필터 설계)

  • Kim, Byoung-Wook;Bang, Jun-Ho;Cho, Seong-Ik;Choi, Seok-Woo;Kim, Dong-Yong
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.57 no.3
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    • pp.255-259
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    • 2008
  • In this paper, a current-mode integrator for low-voltage, low-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS parameter is performed and achieved 44.9dB gain, 15.7MHz unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12MHz cutoff frequency which is suitable for WCDMA baseband block.

A fully-differential bipolar current-controlled current amplifier(CCCA) (완전-차동형 바이폴라 전류-제어 전류 증폭기(CCCA))

  • 손창훈;임동빈;차형우
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.289-292
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    • 2001
  • A Novel fully-differential bipolar current-controlled current amplifier(CCCA) for electrically tunable circuit design at current-mode signal processing were designed. The CCCA was consisted of fully-differential subtracter and fully-differential current gain amplifier. The simulation result shows that the CCCA has current input impedance of 0.5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100$mutextrm{A}$ to 20 ㎃. The power dissipation is 3 mW.

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Design of a Dual Mode Baseband Filter Using the Current-Mode Integrator (전류모드 적분기를 이용한 듀얼 모드 기저대역 필터 설계)

  • Kim, Byoung-Wook;Bang, Jun-Ho;Cho, Seong-Ik;Choi, Seok-Woo;Kim, Dong-Yong
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.57 no.3
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    • pp.260-264
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    • 2008
  • In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

Improvement of Gain and Frequency Characteristics of the CMOS Low-voltage Current-mode Integrator (CMOS 저전압 전류모드 적분기의 이득 및 주파수 특성 개선)

  • Ryu, In-Ho;Song, Je-Ho;Bang, Jun-Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.12
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    • pp.3614-3621
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    • 2009
  • In this paper, A CMOS low-voltage current mode integrator is designed. The designed current-mode integrator is based on linear cascode circuit that is newly proposed in this paper. When it is compared with gain(43.7dB) and unity gain frequency(15.2MHz) of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain(47.8dB) and unity gain frequency(27.8MHz). And a 5th Chebyshev current-mode filter with 7.03MHz cutoff frequency is designed. The designed all circuits are simulated by HSPICE using 1.8V-$0.18{\mu}m$ CMOS technology.

A Dual-Band Through-the-Wall Imaging Radar Receiver Using a Reconfigurable High-Pass Filter

  • Kim, Duksoo;Kim, Byungjoon;Nam, Sangwook
    • Journal of electromagnetic engineering and science
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    • v.16 no.3
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    • pp.164-168
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    • 2016
  • A dual-band through-the-wall imaging radar receiver for a frequency-modulated continuous-wave radar system was designed and fabricated. The operating frequency bands of the receiver are S-band (2-4 GHz) and X-band (8-12 GHz). If the target is behind a wall, wall-reflected waves are rejected by a reconfigurable $G_m-C$ high-pass filter. The filter is designed using a high-order admittance synthesis method, and consists of transconductor circuits and capacitors. The cutoff frequency of the filter can be tuned by changing the reference current. The receiver system is fabricated on a printed circuit board using commercial devices. Measurements show 44.3 dB gain and 3.7 dB noise figure for the S-band input, and 58 dB gain and 3.02 dB noise figure for the X-band input. The cutoff frequency of the filter can be tuned from 0.7 MHz to 2.4 MHz.

Gate length scaling behavior and improved frequency characteristics of In0.8Ga0.2As high-electron-mobility transistor, a core device for sensor and communication applications (센서 및 통신 응용 핵심 소재 In0.8Ga0.2As HEMT 소자의 게이트 길이 스케일링 및 주파수 특성 개선 연구)

  • Jo, Hyeon-Bhin;Kim, Dae-Hyun
    • Journal of Sensor Science and Technology
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    • v.30 no.6
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    • pp.436-440
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    • 2021
  • The impact of the gate length (Lg) on the DC and high-frequency characteristics of indium-rich In0.8Ga0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (LSD) of 0.8 ㎛ with different values of Lg ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (VT) roll-off behavior against Lg was observed clearly, and the maximum transconductance (gm_max) improved as Lg scaled down to 19 nm. In particular, the device with an Lg of 19 nm with an LSD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a gm_max of 2.5 mS/㎛, On resistance (RON) of 261 Ω·㎛, current-gain cutoff frequency (fT) of 738 GHz, and maximum oscillation frequency (fmax) of 492 GHz. The results indicate that the reduction of Lg to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

Wet etching charicteristics of InP in InP/InGaAs HBTs and their fabrication (InP의 습식식각특성과 InP/lnGaAs HBT의 제작)

  • 김강대;박재홍;김용규;황성범;송정근
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.77-80
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    • 2002
  • In this paper, InP-based HBTs have been optimally designed by numerical simulation and fabricated by the self-aligned process. The structure of HBT was designed in terms of the current gain*f$_{max}$ for the base and f$_{T}$*f$_{max}$ for the collector. The designed structure produced the current gain of about 50 and the cutoff frequency and the maximum oscillation frequency of 87GHz and 2940Hz respectively. In addition, we present a study of the vertical and lateral etching of InP with the mask sides parallel to the principal crystallographic axes, [0101 and (001). This etching characteristics arc used to fabricate self-aligned HBT structures with reduced parasitic effects.s.s.s.

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Design of A Current-mode Bandpass Filter in Receiver for High speed PLC Modem (고속 전력선통신 모뎀용 수신단측 전류모드 대역통과 필터 설계)

  • Bang, Jun-Ho;Lee, Woo-Choun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.10
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    • pp.4745-4750
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    • 2012
  • In this paper a $6^{th}$ 1MHz~30MHz bandpass filter for Power line communication(PLC) modem receiver is designed using current mode synthesis method which is good to design the low-voltage and low-power filter. The designed bandpass filter is composed of cascade connecting between $3^{rd}$ Butterworth highpass filter and $3^{rd}$ Chebychev lowpass filter. As a core circuit in the current-mode filter, a current-mode integrator is designed with new architecture which can improve gain and unity gain frequency of the integrator. The gain and the unity gain frequency of the designed integrator is each 32.2dB and 247MHz. And the cutoff frequency of the designed $6^{th}$ bandpass filter can be controlled to 50MHz from 200KHz according to controlling voltage and the power consumption is 2.85mW with supply voltage, 1.8V. The designed bandpass filter was verified using a $0.18{\mu}m$ CMOS parameter.