• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.57-62
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• 1993

In this paper, both feasible power gain and power added efficiency at the operating center frequency of 12 GHz are stressed to design a power FET with double-heterjunction structure. The variable parameters or the design are the unit gate width, the gate length, the doping density of AlGaAs, the AlGaAs thickness, the spacer thickness, the Al mole fraction, and the GaAs well thickness. The results of simulation for the FET with 1.mu.m gate length show that the power gain and the power added efficiency are 10.2 dB and 36.3% at 12GHz, respectively. An extrapolation of the relation between current gain and unilateral gain yields a 17 GHz cutoff frequency and 43GHz maximum frequency of oscillation. The calculation of the current versus voltage characteristics show that the output power of the device is about 0.62W.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.185-197
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• 1996

We have adopted the strain compensated PBH(planar buried heterostructure) - LD in which the MQW active layer consisted of 1.4% compressively strained GainAsP (E$_{g}$ = 0.905eV) wells and 0.7% tensile strained GaInAsP(E$_{g}$ = 1.107eV) barriers grown by metal organic vapor phase epitaxy (MOVPE). We hav einvestigated effects of number of wells and the structure of the separate confinement heterostructure (SCH) layer in the strain-compensated MQW-PBH-LD. The threshold current, the external quantum efficiency, the transparency current density J$_{o}$, and the gain constant .beta. have been evaluated for uncoated MQW-PBH-LD. As the number of wells increases, the internal quantum efficiency and the transparency current density decreases, whereas the gain contant increases. The small width of the SCH layer shows the large internal quantum efficiency. The small internal loss and the large gain constant have been obtained by inserting the large bandgap SCH layer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.900-905
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• 2009

A common drain feedback CMOS wideband LNA with current bleeding and input inductive series-peaking techniques is presented in this paper. DC coupling is adopted between cascode and feedback amplifiers, so that the gain and NF of the LNA can be dynamically controlled by adjusting the bleeding current. The fabricated LNA shows the bandwidth of 2.5 GHz. The high gain mode shows 17.5 dB gain with $1.7{\sim}2.8\;dB$ NF and consumes 27 mW power and the low gain mode has 14 dB gain with $2.7{\sim}4.0\;dB$ NF and dissipates 1.8 mW from 1.8 V supply.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.30-38
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• 1998

In this paper, a new CMOS current-mode integrator is proposed that can apply the basic building block of the low-voltage high frequency current-mode active filter. And tuning circuits that control the gain and unity gain frequency of them is designed. The proposed integrator is composed of the CMOS complementary circuit which can extend transconductance of an integrator. Therefore, the unity gain frequency which is determined transconductance and MOSFET gate capacitance can be expanded by the proposed integrator. The unity gain frequency of the proposed integrator is increased about two times larger than that of the conventional continuous-time integrator with NMOS-gm. And also, cut-off frequency and gain of the active filter can be controlled with the designed tuning circuit. From the result, we can reduce errors on fabrication. And then, 3rd-order low-pass active filter is designed as an application circuits. These results are verified by the small signal analysis and the 0.8$\mu\textrm{m}$ parameter HSPICE simulation.

• Korean Journal of Optics and Photonics
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• v.2 no.2
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• pp.67-73
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• 1991

The unsaturated signal gain, signal gain bandwidth, and saturation power which are important parameters determining characteristics of the semiconductor laser amplifier were measured for an AlGaAs Fabry-Perot cavity type laser amplifier and compared with the results of Fabry-Perot formula. The unsaturated signal gain 25 dB is obtained near oscillation thereshold current at $0.7\mu\textrmW$ input power. The corresponding signal gain bandwidth was about 3 GHz. Also. We measured the variation of the saturation signal gain and saturation power.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4745-4750
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• 2012

In this paper a $6^{th}$ 1MHz~30MHz bandpass filter for Power line communication(PLC) modem receiver is designed using current mode synthesis method which is good to design the low-voltage and low-power filter. The designed bandpass filter is composed of cascade connecting between $3^{rd}$ Butterworth highpass filter and $3^{rd}$ Chebychev lowpass filter. As a core circuit in the current-mode filter, a current-mode integrator is designed with new architecture which can improve gain and unity gain frequency of the integrator. The gain and the unity gain frequency of the designed integrator is each 32.2dB and 247MHz. And the cutoff frequency of the designed $6^{th}$ bandpass filter can be controlled to 50MHz from 200KHz according to controlling voltage and the power consumption is 2.85mW with supply voltage, 1.8V. The designed bandpass filter was verified using a $0.18{\mu}m$ CMOS parameter.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.260-264
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• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• ETRI Journal
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• v.44 no.4
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• pp.695-707
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• 2022

As for the insufficient nature of the fossil fuel resources, the renewable energies as alternative fuels are imperative and highly heeded. To deliver the required electric power to the industrial and domestic consumers from DC renewable energy sources like fuel cell (FC), the power converter operates as an adjustable interface device. This paper suggests a new boost structure to provide the required voltage with wide range gain for FC power source. The proposed structure based on the boost converter and the quazi network, the so-called SBQN, can effectively enhance the FC functionality against its high operational sensitivity to experience low current ripple and also propagate voltage and current with low stress across its semiconductors. Furthermore, the switching power losses have been decreased to make this structure more durable. A full operational analysis of the proposed SBQN and its advantages over the conventional and famous structures has been compared and explained. Furthermore, a prototype of the single-phase converter has been constructed and tested in the laboratory.