• Journal of the Korean Society of Industry Convergence
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• v.20 no.2
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• pp.97-104
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• 2017

In the present industrial field, the demand for the development of the solar power source device and the charging device for the solar cell is gradually increasing. The solar charger is largely divided into a DC-DC converter that converts the voltage generated from the sunlight to a charging voltage, and a battery and a charger that are charged with an actual battery. The conventional charger topology is used either as a Buck converter or a Boost converter alone, which has the disadvantage that the battery can not always be charged to the desired maximum power as input and output conditions change. Although studies using a topology capable of boosting and stepping have been carried out, Buck-Boost converters or Sepic converters with relatively low efficiency have been used. In this paper, we propose a new Buck Boost combination power converter topology structure that can use Buck converter and Boost converter at the same time to improve inductor current ripple and power converter efficiency caused by wide voltage control range like solar charger.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.25-26
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• 2015

Inductive Power Transfer (IPT) method becomes more and more popular for the Electric Vehicle (EV) battery charger due to its convenience and safety in comparison with plugged-in charger. In recent years, Lithium batteries are increasingly used in EVs and Constant Current/Constant Voltage (CC/CV) charge needs to be adopted for the high efficiency charge. However, it is not easy to design the IPT Battery Charger which can charge the battery with CC/CV charge under the wide range of load variation due to the wide range of variation in its operating frequency. This paper propose a new design and control method which makes it possible to implement the CC/CV mode charge with minimum frequency variation (less than 1kHz) during all over the charge process. A 6.6kW prototype charge has been implemented and 96.1% efficiency was achieved with 20cm air gap between the coils.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• Annual Conference of KIPS
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• 2022.11a
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• pp.625-627
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• 2022

In the construction and development of modern industrial production technology, the traditional technology management mode is faced with many problems such as low qualification rates and high application costs. In the research, an improved workpiece defect detection method based on deep learning is proposed, which can control the application cost and improve the detection efficiency of irregular defects. Based on the research of the current situation of deep learning applications, this paper uses the improved Faster R-CNN network structure model as the core detection algorithm to automatically locate and classify the defect areas of the workpiece. Firstly, the robustness of the model was improved by appropriately changing the depth and the number of channels of the backbone network, and the hyperparameters of the improved model were adjusted. Then the deformable convolution is added to improve the detection ability of irregular defects. The final experimental results show that this method's average detection accuracy (mAP) is 4.5% higher than that of other methods. The model with anchor size and aspect ratio (65,129,257,519) and (0.2,0.5,1,1) has the highest defect recognition rate, and the detection accuracy reaches 93.88%.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.179-184
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• 2019

In many countries, such as developing countries where electricity is scarce, small wind turbines in the form of Off Grid are an effective solution to solve power supply problems. In some countries, the expansion of power systems and the decline of electricity-intensive areas have led to the use of small wind power in urban road lighting, mobile communications base stations, aquaculture and seawater desalination. With this change, the size of the small wind power industry is expected to have greater potential than large-scale wind power. In the case of small wind power generators, the generator is controlled at a variable speed, and the voltage and current generated by the generator have many harmonic components. To solve this problem, the AC to DC converter to be studied in this paper is a three-phase step-up type converter with a single switch. The inductor current is controlled in discontinuous mode, and has a characteristic of having a unit power factor by eliminating the harmonic of the input current. The proposed converter is composed of LCL filter and three phase rectification boost converter at the input stage and a single phase full bridge for grid connection. It is a control system with energy storage system(ESS) that the system stabilization can be pursued against the electric power.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.29-36
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• 2000

The principle and design of two-stage CMOS operational amplifier with rail-to-rail input and class-AB output stage is presented. The rail-to-rail input stage shows almost constant transconductance independent of the common mode input voltage range in global transistor operation region. This new technique does not make use of accurate current-voltage relationship of MOS transistors. Hence it was achieved by using simple linear relationship of currents. The simulated transconductance variation using SPICE is less the 4.3%. The proposed global two-stage opamp can operate both in strong inversion and in weak inversion. Class AB output stage proposed also has a full output voltage swing and a well-defined quiescent current that does not depend on power supply voltage. Since feedback class- AB control is used, it is expected that this output stage can be operating in extremely low voltage. The variation of DC-gain and unity-gain frequency is each 4.2% and 12%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.100-105
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• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.11-116
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• 2000

A topology decreased switching loss and voltage stress by zero voltage switching is presented in this paper. Generally, Switching mode converting productes voltage stress and power losses due to excessive voltage and current. which affect to performance of power supply and reduce overall efficiency of equipments. Virtually, In flyback converter, transient peak voltage and current at switcher are generated by parasitic elements. To solve these problems, present ZVS flyback converter topology applied a auxiliary circuit. Incorporation of auxiliary circuit into a conventional flyback topology serves to reduce power losses and to minimize switching voltage stress. Snubber capacitor in auxiliary circuit serves ZVS state by control voltage variable time at turn on and off of main switch, then reduces voltage stress and power losses. The proposed converter has lossless switching in variable load condition with wide range. A detailed analysis of the circuit is presented and the operation procedure is illustrated. A (50W 100kHz prototype) ZVS flyback converter using a auxiliary circuit is built which shows an efficiency improvement as compared to a conventional hard switching flyback converter.