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A Low Area and High Efficiency SMPS with a PWM Generator Based on a Pseudo Relaxation-Oscillating Technique

Pseudo Relaxation-Oscillating 기법의 PWM 발생기를 이용한 저면적, 고효율 SMPS

  • Lim, Ji-Hoon (Department of Electronic Engineering, Soongsil University, Automotive Semiconductor R&D Center, Hyundai Autron) ;
  • Wee, Jae-Kyung (Department of Electronic Engineering, Soongsil University, Automotive Semiconductor R&D Center, Hyundai Autron) ;
  • Song, Inchae (Department of Electronic Engineering, Soongsil University, Automotive Semiconductor R&D Center, Hyundai Autron)
  • 임지훈 (숭실대학교 전자공학과, 현대오트론 차량반도체개발센터) ;
  • 위재경 (숭실대학교 전자공학과, 현대오트론 차량반도체개발센터) ;
  • 송인채 (숭실대학교 전자공학과, 현대오트론 차량반도체개발센터)
  • Received : 2013.06.20
  • Published : 2013.11.25

Abstract

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

본 논문에서는 새로운 기법의 PWM 발생기를 이용한 저면적, 고효율 SMPS를 제안한다. 제안된 회로에서 PWM의 duty ratio는 pseudo relaxation-oscillation technique를 이용한 PWM 발생기의 내부 커패시터 전압 기울기를 제어하는 방식으로 결정된다. 기존의 SMPS들에 비해, 제안된 제어 방식은 loop bandwidth 보상을 위해 기존의 아날로그 제어방식의 SMPS에서 요구되는 필터회로나 디지털 제어방식의 SMPS에서 요구되는 디지털 compensator가 필요 없기 때문에 단순한 구조로 구성된다. 또한, 제안된 회로는 PWM 발생기의 내부 캐패시터 용량 변화를 통해 1MHz~10MHz까지 스위칭 주파수를 사용자가 선택할 수 있다. 시뮬레이션 수행결과 제안된 SMPS는 10MHz 스위칭 주파수를 선택했을 때 내부회로에서 소모되는 전류는 최대 2.7mA, 파워 Trail을 제외한 전체 시스템의 전류 소모는 15mA였다. 또한, 제안된 SMPS는 시뮬레이션으로 3.3V출력에서 9mV의 최대 리플 전압이 발생하였다. 본 논문에서는 동부하이텍 BCD $0.35{\mu}m$ 공정 파라미터를 이용한 시뮬레이션 및 칩 테스트를 통해 제안된 회로를 검증하였다.

Keywords

References

  1. Pui-Kei Leong, Chun-Hung Yang, Chi-Wai Leng, and Chien-Hung Tsai, "Design and implementation of sigma-delta DPWM controller for switching converter," Circuits and Systems, ISCAS, IEEE International Symposium on, pp.3074-3077, May. 2009.
  2. H.H. Ahmad, and B. Bakkaloglu, "A 300mA 14mV-ripple digitally controlled buck converter using frequency domain ${\Delta}{\Sigma}$ ADC and hybrid PWM generator," International Solid-State Circuits Conference, ISSCC, IEEE International Conference on, pp.202-203, Feb. 2010.
  3. Brad Bryant,andMarianK.Kazimierczuk,"Modeling the Closed-Current Loop of PWM Boost DC-DC Converters Operating in CCM With Peak Current-Mode Control," IEEE Trans. Circuits and systems, Vol.53, pp.2404-2412, 2005.
  4. Reza Ahmadi, Darren Paschedag, and Mehdi Ferdowsi, "Closed-loop Input and Output Impedances of DC-DC Switching Converters operating in Voltage and Current Mode Control," Industrial Electronics Society, IECON, IEEE conference on, pp.2311-2316, 2010.
  5. Yanxia Gao, Shaofeng Zhang, Yanping Xu, and Shuibao Gao, "Analysis and comparison of three implementation methodologies for high-resolution DPWM", IEEE International Conference on Power Electronics Systems and Applications, pp. 1-7, 2009.
  6. Yanxia Gao, Shuibao Guo, Yanping Xu, Shi Xuefang Lin, and B. Allard, "FPGA-Based DPWM for Digitally Controlled High-Frequency DC-DC SMPS," Power Electronics Systems and Applications, PESA, IEEE Conference on, pp1-7, May. 2009.
  7. Sangduk Yu, Youngchan Choi, Kichang Jang Jungsoo Choi, Jungeui Park, Wooju Jeong, Joongho Choi, "Design of Digitally-Controlled Synchronous Buck Converter", IEEK 2008 SOC conference, pp. 17-20, May, 2008.
  8. Ji-Hoon Lim, Won-Young Jung, Yong-Ju Kim, Inchae Song, and Jae-Kyung Wee, "A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique", IEICE TRANSACTIONS on Electronics Vol.E96-C No.2 pp.277-284, 2013. https://doi.org/10.1587/transele.E96.C.277
  9. http://www.abracon.com/Magnetics/new/ASPI-0412S.pdf
  10. http://www.johansondielectrics.com/images/stories/surface-mount/tanceram/JDI_Tanceram_High-Cap-2012-04.pdf
  11. Maity, A., Patra, A., Yamamura, N., Knight, J., "Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications", VLSI Design, 24th International Conference on pp.316-321, 2011.
  12. Chin-Long Wey, Chan-I Chiu, Kun-Chun Chang, Chung-Hsien Hsu, Gang-Neng Sung, "Design of ultra-wide-load, high-efficient DC-DC buck converters", Electronics, Circuits and System, ICECS, IEEE Conference on, pp.297-300, 2011
  13. A. Emira, F. Carr, H. Elwan, R.H Mekky, "High voltage tolerant integrated Buck converter in 65nm 2.5V CMOS", Circuits and Systems, ISCAS, IEEE International Symposium on, pp.2405-2408, 2009.
  14. A. Ehrhart, B. Wicht, M. Lin, Yung-Sheng Huang, "Adaptive pulse skipping and adaptive compensation capacitance techniques in current-mode buck-boost DC-DC converters for fast transient response", Power Electronics and Drive Systems, PEDS, IEEE International Conference on, pp.273-378, 2013.