• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.71-71
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• 2012

As the critical dimensions of integrated circuits are scaled down, the line width and spacing between the metal interconnects are made smaller. The dielectric film used as insulation between the metal lines contributes to the resistance-capacitance (RC) time constant that governs the device speed. If the RC time delay, cross talk and lowering the power dissipation are to be reduced, the intermetal dielectric (IMD) films should have a low dielectric constant. The introduction of Cu and low-k dielectrics has incrementally improved the situation as compared to the conventional $Al/SiO_2$ technology by reducing both the resistivity and the capacitance between interconnects. Some of the potential candidate materials to be used as an ILD are organic and inorganic precursors such as hydrogensilsequioxane (HSQ), silsesquioxane (SSQ), methylsilsisequioxane (MSQ) and carbon doped silicon oxide (SiOCH), It has been shown that organic functional groups can dramatically decrease dielectric constant by increasing the free volume of films. Recently, various inorganic precursors have been used to prepare the SiOCH films. The k value of the material depends on the number of $CH_3$ groups built into the structure since they lower both polarity and density of the material by steric hindrance, which the replacement of Si-O bonds with Si-$CH_3$ (methyl group) bonds causes bulk porosity due to the formation of nano-sized voids within the silicon oxide matrix. In this talk, we will be introduce some properties of SiOC(-H) thin films deposited with the dimethyldimethoxysilane (DMDMS: $C_4H_{12}O_2Si$) and oxygen as precursors by using plasma-enhanced chemical vapor deposition with and without ultraviolet (UV) irradiation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.114-121
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• 2003

Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.78-78
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• 2007

In semiconductor devices, Cu has been used for the formation of multilevel metal interconnects by the damascene technique. Also lower dielectric constant materials is needed for the below 65 nm technology node. However, the low-k materials has porous structure and they can be easily damaged by high down pressure during conventional CMP. Also, Cu surface are vulnerable to have surface scratches by abrasive particles in CMP slurry. In order to overcome these technical difficulties in CMP, electro-chemical mechanical planarization (ECMP) has been introduced. ECMP uses abrasive free electrolyte, soft pad and low down-force. Especially, electrolyte is an important process factor in ECMP. The purpose of this study was to characterize KOH and $KNO_3$ based electrolytes on electro-chemical mechanical. planarization. Also, the effect of additives such as an organic acid and oxidizer on ECMP behavior was investigated. The removal rate and static etch rate were measured to evaluate the effect of electro chemical reaction.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.95-99
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• 2008

Cu has been used for metallic interconnects in ULSI applications because of its lower resistivity according to the scaling down of semiconductor devices. The resistivity of Cu lines will affect the RC delay and will limit signal propagation in integrated circuits. We investigated the electrolyte effects of the electroplating solution in the resistivity value of Cu films grown by electroplating deposition (EPD). The resistivity was measured with a four-point probe and the material properties were investigated with XRD (X-ray Diffraction), AFM (Atomic Force Microscope), FE-SEM (Field Emission Scanning Electron Microscope) and XPS (X-ray Photoelectron Spectroscopy). From these experimental results, we found that the electrolyte condition plays an Important role in formation of Cu film with lower resistivity by EPD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.546-546
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• 2008

Copper (Cu) Chemical mechanical polishing (CMP) has been an essential process for Cu wifing of DRAM and NAND flash memory beyond 45nm. Copper has been employed as ideal material for interconnect and metal line due to the low resistivity and high resistant to electro-migration. Damascene process is currently used in conjunction with CMP in the fabrication of multi-level copper interconnects for advanced logic and memory devices. Cu CMP involves removal of material by the combination of chemical and mechanical action. Chemicals in slurry aid in material removal by modifying the surface film while abrasion between the particles, pad, and the modified film facilitates mechanical removal. In our research, we emphasized on the role of chemical effect of slurry on Cu CMP, especially on the effect of amine functional group on removal rate selectivity between Cu and Tantalum-nitride (TaN) film. We investigated the two different kinds of complexing agent both with amine functional group. On the one hand, Polyacrylamide as a polymer affected the stability of abrasive, viscosity of slurry and the corrosion current of copper film especially at high concentration. At higher concentration, the aggregation of abrasive particles was suppressed by the steric effect of PAM, thus showed higher fraction of small particle distribution. It also showed a fluctuation behavior of the viscosity of slurry at high shear rate due to transformation of polymer chain. Also, because of forming thick passivation layer on the surface of Cu film, the diffusion of oxidant to the Cu surface was inhibited; therefore, the corrosion current with 0.7wt% PAM was smaller than that without PAM. the polishing rate of Cu film slightly increased up to 0.3wt%, then decreased with increasing of PAM concentration. On the contrary, the polishing rate of TaN film was strongly suppressed and saturated with increasing of PAM concentration at 0.3wt%. We also studied the electrostatic interaction between abrasive particle and Cu/TaN film with different PAM concentration. On the other hand, amino-methyl-propanol (AMP) as a single molecule does not affect the stability, rheological and corrosion behavior of the slurry as the polymer PAM. The polishing behavior of TaN film and selectivity with AMP appeared the similar trend to the slurry with PAM. The polishing behavior of Cu film with AMP, however, was quite different with that of PAM. We assume this difference was originated from different compactness of surface passivation layer on the Cu film under the same concentration due to the different molecular weight of PAM and AMP.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.99.1-99.1
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• 2016

The materials for an electronic packaging provide diverse important functions including electrical contact to transfer signals from devices, isolation to protect from the environment and a path for heat conduction away from the devices. The packaging materials composed of metals, ceramics, polymers or combinations are crucial to the device operating properly and reliably. The demand of effective charge and heat transfer continuous to be challenge for the high-speed and high-power devices. Nanomaterials including graphene, carbon nanotube and boron nitride, have been designed for the purpose of exploiting the high thermal, electrical and mechanical properties by combining in the matrix of metal or polymer. In addition, considering the inherent electrical and surface properties of graphene, it is expected that graphene would be a good candidate for the surface layer of a template in the electroforming process. In this talk, I will present recent our on-going works in nanomaterials for microelectronic packaging: 1) porous graphene/Cu for heat dissipations, 2) carbon-metal composites for interconnects and 3) nanomaterials-epoxy composites as a thermal interface materials for electronic packaging.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.2
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• pp.36-44
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• 2024

Copper electrodeposition technology is essential for producing copper films and interconnects in the microelectronics industries including semiconductor packaging, semiconductors and secondary battery, and there are extensive efforts to control the microstructure of these films and interconnects. In this study, we investigated the influence of crystallographic orientation on the local plastic deformation of copper films for secondary batteries deformed by uniaxial tensile load. Crystallographic orientation maps of two electrodeposited copper films with different textures were measured using an electron backscatter diffraction (EBSD) system and then used as initial conditions for crystal plasticity finite element analysis to predict the local plastic deformation behavior within the films during uniaxial tension deformation. Through these processes, the changes of the local plastic deformation behavior and texture of the films were traced according to the tensile strain, and the crystal orientations leading to the inhomogeneous plastic deformation were identified.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Korean Vacuum Society
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• v.20 no.2
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• pp.155-163
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• 2011

Carbon nanotubes (CNT) have been attracted much attention since they have been expected to be used in various areas by virtue of their outstanding physical, electrical, and chemical properties. In order to make full use of their prominent electric conductivity in some areas such as electron emission sources, device interconnects, and electrodes in energy storage devices, direct growth of CNT with vertical alignment is definitely beneficial issue because they can maintain mechanical stability and high conductivity at the interface between substrates. Here, we report direct growth of vertically aligned CNT (VCNT) on Cu foils using thermal chemical vapor deposition and characterize the field emission property of the VCNT. The VCNT's height was controlled by changing the growth temperature, growth time, and catalytic layer thickness. Optimum growth condition was found to be $800^{\circ}C$ for 20 min with acetylene and hydrogen mixtures on Fe catalytic layer of 1 nm thick. The diameter of VCNT grown was smaller than that of usual multi walled CNT. Based on the result of field emission characterization, we concluded that the VCNT on Cu foils can be useful in various potential applications where high conductivity through the interface between CNT and substrate is required.

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.