• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.123-124
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• 2005

We investigated the effect of a Ta/TaN Cu diffusion barrier existence on the reliability and the electrical performance of Cu dual-damascene interconnects. A high EM performance in Cu dual-damascene structure was observed the BCV(barrier contact via) interconnect structure to remain Ta/TaN barrier layer. Via resistance was decreased DCV interconnect structure by bottomless process. This structure considers that DCV interconnect structure has lower activation energy and higher current density than BCV interconnect structure. The EM failures by BCV via structure were formed at via hole, but DCV via structure was formed EM fail at the D2 line. In order to improve the EM characteristic of DCV interconnect structure by bottomless process, after Ta/TaN diffusion barrier layer in via bottom is removed by Ar+ resputtering process, it is desirable that Ta thickness is thickly made by Ta flash process.

• 마이크로전자및패키징학회지
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• 제21권3호
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• pp.1-6
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• 2014

차세대 전자소자는 입출력(I/O) 핀 수의 증가, 전력소모의 감소, 소형화 등으로 인해 fine-pitch 배선 시스템이 요구되고 있다. Fine-pitch 특히 10 um 이하의 fine-pitch에서는 기존의 무연솔더나 Cu pillar/solder cap 구조를 사용할 수 없기 때문에 Cu-to-Cu bumpless 배선 시스템은 2D/3D 소자 구조에서 매우 필요한 기술이라 하겠다. Bumpless 배선 기술로는 BBUL 기술, 접착제를 이용한 WOW의 본딩 기술, SAB 기술, SAM 기술, 그리고 Cu-to-Cu 열압착 본딩 기술 등이 연구되고 있다. Fine-pitch Cu-to-Cu interconnect 기술은 연결 방법에 상관없이 Cu 층의 불순물을 제거하는 표면 처리 공정, 표면 활성화, 표면 평탄도 및 거칠기가 매우 중요한 요소라 하겠다.

• ETRI Journal
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• 제45권5호
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• pp.910-921
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• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 국제표면실장 및 인쇄회로기판 생산기자재전:전자패키지기술세미나
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• pp.37-59
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• 2004

In the case of Ni/Au finished pad on the package side, the solder joint of SnAgCu system can bring brittle fracture under impact load such as drop test. Therefore, it's difficult to prevent the brittle fracture of lead-free solder, by controlling Cu content. The failure locus existing on the interface between $(Ni,Cu)_3Sn_4\;and\;(Cu,Ni)_6Sn_5$ IMC layers must be changed to other site in order to avoid brittle fracture due to impact load. It was not found any clear evidence that there were two IMC layers exist. But it was strongly assumed these were two layers which have different Cu-Ni composition. From the above analysis it was assumed that Cu atom in the solder alloy or substrate seemed to affect IMC composition and cause to IMC brittle fracture.

• 한국전기전자재료학회논문지
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• 제20권3호
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• pp.213-217
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• 2007

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

• 마이크로전자및패키징학회지
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• 제6권4호
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• pp.1-7
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• 1999

MCM-D 기판에 수동소자를 내장시키는 공정을 개발하였다. MCM-D 기판은 Cu/감광성 BCB를 각각 금속배선 및 절연막 재료로 사용하였고, 금속배선은 Ti/cu를 각각 1000$\AA$/3000$\AA$으로 스퍼터한 후 fountain 방식으로 전기 도금하여 3 um Cu를 형성하였으며, BCB 층에 신뢰성있는 비아형성을 위하여 BCB의 공정특성과 $C_2F_6$를 사용한 플라즈마 cleaning영향을 AES로 분석하였다. 이 실험에서 제작한 MCM-D 기판은 절연막과 금속배선 층이 각각 5개, 4개 층으로 구성되는데 저항은 2번째 절연막 위에 thermal evaporator 방식으로 NiCr을 600$\AA$증착하여 시트저항이 21 $\Omega$/sq가 되게 형성하였고. 인덕터는 coplanar 구조로 3, 4번째 금속배선층에 형성하였으며, 커패시터는 절연막으로 PECVD $Si_3N_4$를 900$\AA$증착한 후 1, 2번째 금속배선층에 형성하여 88nF/$\textrm {cm}^2$의 커패시턴스를 얻었다. 이 공정은 PECVD $Si_3N_4$와 thermal evaporation NiCr 공정을 이용함으로써 기존의 반도체 공정을 이용하여 MCM-D 기판에 수동소자를 안정적으로 내장시킬 수 있었다.

• 한국결정학회지
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• 제12권4호
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• pp.233-238
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• 2001

1㎛ 이하로 집속된 방사광원으로부터의 x-선을 이용하여 새로운 분석법인 x-선 미세회절(x-ray microdiffraction)을 사용하면 다결정시료 내 grain들의 방위나 strain의 국지적 분포를 정밀하게 측정할 수 있다. 포항가속기연구소 방사광원의 x-ray microbeam 실험 장치를 사용하여 찍은 Laue 사진을 측별히 쓰여진 분석 software를 이용하여 분석함으로써 고집적회로에 쓰이는것과 같은 방법으로 제작된 Si wafer 상의 다른 선폭의 구리 도선들이 가지는 texture 를 밝혀내었다. 실험시 x-ray빔의 크기는 2×3㎛²정도이었으며, 분석 결과에의하면 선폭 1㎛도선에서는 grain들이 방위가 특정한 방향성이 없는 반면, 선폭 20㎛도선의 중앙부분에서는 〈111〉fiber texture 가 관측되었다. Grain들의 크기는 선폭 1㎛의도선에서 2∼5㎛, 선폭 20㎛의도선에서는 6∼8㎛로 측정되었다.

• 한국재료학회지
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• 제15권11호
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• pp.735-740
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• 2005

The phase transformation of Ni-B diffusion barrier by Cu diffusion was studied. The Ni-B diffusion barrier, thickness of 10(Inn, was electrolessly deposited on the electroplated Cu interconnect. The specimens were annealed either in Ar atmosphere or in $H_2$ atmosphere from $300^{\circ}C\;to\;800^{\circ}C$ for 30min, respectively. Although the Ni-B coated specimens showed the decomposition of $Ni_3B$ above $400^{\circ}C$ in both Ar atmosphere and $H_2$ atmosphere, Ni-B powders did not show the decomposition of $Ni_3B$. The $Ni_3B$ was decomposed to Ni and B in hi atmospherr: and the metallic Ni formed the solid solution with Cu and the free B was oxidized to $B_2O_3$. However, both the boron hydride and free B were not observed in the diffusion barrier after the annealing in $H_2$ atmos There. These results revealed that the decomposition of $Ni_3B$ by Cu made the Cu diffusion continued toward the Ni-B diffusion barrier.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2005년도 추계학술발표회 및 workshop
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• pp.132-133
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• 2005