• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.123-124
• /
• 2005

We investigated the effect of a Ta/TaN Cu diffusion barrier existence on the reliability and the electrical performance of Cu dual-damascene interconnects. A high EM performance in Cu dual-damascene structure was observed the BCV(barrier contact via) interconnect structure to remain Ta/TaN barrier layer. Via resistance was decreased DCV interconnect structure by bottomless process. This structure considers that DCV interconnect structure has lower activation energy and higher current density than BCV interconnect structure. The EM failures by BCV via structure were formed at via hole, but DCV via structure was formed EM fail at the D2 line. In order to improve the EM characteristic of DCV interconnect structure by bottomless process, after Ta/TaN diffusion barrier layer in via bottom is removed by Ar+ resputtering process, it is desirable that Ta thickness is thickly made by Ta flash process.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.3
• /
• pp.1-6
• /
• 2014

The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

• ETRI Journal
• /
• v.45 no.5
• /
• pp.910-921
• /
• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2004.02a
• /
• pp.37-59
• /
• 2004

In the case of Ni/Au finished pad on the package side, the solder joint of SnAgCu system can bring brittle fracture under impact load such as drop test. Therefore, it's difficult to prevent the brittle fracture of lead-free solder, by controlling Cu content. The failure locus existing on the interface between $(Ni,Cu)_3Sn_4\;and\;(Cu,Ni)_6Sn_5$ IMC layers must be changed to other site in order to avoid brittle fracture due to impact load. It was not found any clear evidence that there were two IMC layers exist. But it was strongly assumed these were two layers which have different Cu-Ni composition. From the above analysis it was assumed that Cu atom in the solder alloy or substrate seemed to affect IMC composition and cause to IMC brittle fracture.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.3
• /
• pp.213-217
• /
• 2007

Copper has been used as an interconnect material in the fabrication of semiconductor devices, because of its higher electrical conductivity and superior electro-migration resistance. Chemical mechanical polishing(CMP) technique is required to planarize the overburden Cu film in an interconnect process. Various problems such as dishing, erosion, and delamination are caused by the high pressure and chemical effects in the Cu CMP process. But these problems have to be solved for the fabrication of the next generation semiconductor devices. Therefore, new process which is electro-chemical mechanical polishing(ECMP) or electro-chemical mechanical planarization was introduced to solve the technical difficulties and problems in CMP process. In the ECMP process, Cu ions are dissolved electrochemically by the applying an anodic potential energy on the Cu surface in an electrolyte. And then, Cu complex layer are mechanically removed by the mechanical effects between pad and abrasive. This paper focuses on the manufacturing of ECMP system and its process. ECMP equipment which has better performance and stability was manufactured for the planarization process.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.4
• /
• pp.1-7
• /
• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Korean Journal of Crystallography
• /
• v.12 no.4
• /
• pp.233-238
• /
• 2001

X-ray microdiffraction which uses x-ray beam focused down to a micron size from synchrotron radiation sources allow precision measurements of local orientation and strain variations in polycrystalline materials. Using x-ray microdiffraction setup at Pohang Light Source, we investigated the tex-ture of Cu interconnects with various widths on Si wafer by collecting Laue images and focused to about 2×3㎛ ² in size. Our results show that 1㎛ wide Cu interconnect had grains in rather ran- dom orientation. On the other hand the 20㎛ wide interconnects showed a 〈111〉fiber texture near the center. The grains were 2∼5㎛ long at the 1㎛ wide interconnect and 6∼8㎛ in size at the 20㎛ wide interconnect.

• Korean Journal of Materials Research
• /
• v.15 no.11
• /
• pp.735-740
• /
• 2005

The phase transformation of Ni-B diffusion barrier by Cu diffusion was studied. The Ni-B diffusion barrier, thickness of 10(Inn, was electrolessly deposited on the electroplated Cu interconnect. The specimens were annealed either in Ar atmosphere or in $H_2$ atmosphere from $300^{\circ}C\;to\;800^{\circ}C$ for 30min, respectively. Although the Ni-B coated specimens showed the decomposition of $Ni_3B$ above $400^{\circ}C$ in both Ar atmosphere and $H_2$ atmosphere, Ni-B powders did not show the decomposition of $Ni_3B$. The $Ni_3B$ was decomposed to Ni and B in hi atmospherr: and the metallic Ni formed the solid solution with Cu and the free B was oxidized to $B_2O_3$. However, both the boron hydride and free B were not observed in the diffusion barrier after the annealing in $H_2$ atmos There. These results revealed that the decomposition of $Ni_3B$ by Cu made the Cu diffusion continued toward the Ni-B diffusion barrier.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.1
• /
• pp.17-24
• /
• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2005.11a
• /
• pp.132-133
• /
• 2005