• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1300-1303
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• 2004

Copper는 낮은 저항률과 높은 Electromigration 저항 때문에 반도체 소자에 배선 재료로 사용된다. CMP 공정을 이용 하여 Cu wafer의 여러 가지 특성을 파악하기에는 wafer의 소모량이 많고 고가가의 비용이 예상 되므로, 본 논문에서는 비용절감을 위하여 wafer를 Disc로 대체 하고자 실험을 진행 하였고 Cu wafer와 Disc의 비료 방법은 우선 PM-5 (Genitech. co) 장비를 이용하여 removal rate의 차이점을 알 아 보았으며, 서로의 etch rate을 reomval rate과 비교하였다. EG&G 273A를 통하여 Cu wafer와 disc의 corrosion potential과 $R_p$ (Polarization resistance)값을 서로 비교 하였다. 이 논문에서는 이러한 것들을 서로 비교 하여, Cu wafer와 disc에서의 상관관계를 알고자 하였으며, 만약에 Cu wafer와 disc의 특성이 비슷하다면, Cu wafer 대신에 disc를 이용 하여 실험하여도 되는지에 관하여 조사 하였다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.81-85
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• 2013

Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1292-1295
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• 2004

본 연구는 Cu CMP공정 중 알루미나 연마입자의 wafer 표면에서의 점착과 오염을 AFM (Atomic Force Microscopy)을 사용하여 슬러리내에서 점착력 측정과 실제 연마 후 wafer 표면의 오염을 실험적으로 비교 평가하였다. 연마입자의 adhesionn force 측정에 있어서도 역시 wafer들의 zetapotential 결과와 잘 일치하였으며, 모든 wafer 종류에 관계없이, 산성 영역에서 염기성영역의 슬러리가 적용됨에 따라 adhesion force가 작아짐을 확인할 수 있었다. 특히 FSG wafer의 zetapotential 결과는 비록 산성 분위기에서는 양성 전하값을 나타내었으나, 염기성 분위기의 pH에서는 급격하게 음성 전하값을 나타내었고, 이는 adhesionn force결과와 FESEM 결과와 잘 일치하였다.

• Bulletin of the Korean Chemical Society
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• v.32 no.7
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• pp.2227-2232
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• 2011

The new metrology, Advanced Poly-silicon Ultra-Trace Profiling (APUTP), was developed for measuring bulk Cu and Ni in heavily boron-doped silicon wafers. A Ni recovery yield of 98.8% and a Cu recovery yield of 96.0% were achieved by optimizing the vapor phase etching and the wafer surface scanning conditions, following capture of Cu and Ni by the poly-silicon layer. A lower limit of detection (LOD) than previous techniques could be achieved using the mixture vapor etching method. This method can be used to indicate the amount of Cu and Ni resulting from bulk contamination in heavily boron-doped silicon wafers during wafer manufacturing. It was found that a higher degree of bulk Ni contamination arose during alkaline etching of heavily boron-doped silicon wafers compared with lightly boron-doped silicon wafers. In addition, it was proven that bulk Cu contamination was easily introduced in the heavily boron-doped silicon wafer by polishing the wafer with a slurry containing Cu in the presence of amine additives.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.434-437
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• 2005

Chemical Mechanical Polishing (CMP) has become an essential step in the overall semiconductor wafer fabrication technology. In general, CMP is a surface planarization method in which a silicon wafer is rotated against a polishing pad in the presence of slurry under pressure. The polishing pad, generally a polyurethane-based material, consists of polymeric foam cell walls, which aid in removal of the reaction products at the wafer interface. It has been found that the material removal rate of any polishing pad decreases due to the so-called 'pad glazing' after several wafer lots have been processed. Therefore, the pad restoration and conditioning has become essential in CMP processes to keep the urethane polishing pad at the proper friction coefficient and to allow effective slurry transport to the wafer surface. Diamond pad conditioner employs a single layer of brazed bonded diamond crystals. Due to the corrosive nature of the polishing slurry required in low pH metal CMP such as copper, it is essential to minimize the possibility of chemical interaction between very low pH slurry (pH <2) and the bond alloy. In this paper, we report an exceptional protective coated conditioner for in-situ pad conditioning in low pH Cu CMP process. The protective Cr-coated conditioner has been tested in slurry with pH levels as low as 1.5 without bond degradation.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.63-68
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• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.

• Electrical & Electronic Materials
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• v.9 no.7
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• pp.727-732
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• 1996

In the present paper, the Cu films 4.mu.m thick were deposited by RF magnetron sputtering method on Si wafer. The Cu films deposited at a condition of 100W, 10mtorr exhibited a low electrical resistivity of 2.3.mu..ohm..cm and densed microstructure, poor adhesion. The Cu films grown by 200W, 20mtorr showed a good adhesion property and higher electrical resistivity of 7.mu..ohm..cm because of porous columnar microstructure. Therefore, The Cu films were deposited by double layer deposition method using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adhesion, and reflectance in the CU films [C $U_{4-d}$(low resistivity) / C $U_{d}$(high adhesion) / Si-wafer] on the thickness of d has been investigated. The films formed with this deposition methods had the low electrical resistivity of about 2.6.mu..ohm..cm and high adhesion of about 700g/cm.m.m.