• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.136-136
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• 2012

Cu 박막이 pyrophosphate baths로부터 전기도금공정에 의해 제조되었으며, 전류밀도 및 도금온도가 Cu 박막의 특성에 미치는 영향을 조사하였다. 전류 밀도 및 도금온도 모두 전류효율, 잔류응력, 표면형상, 미세조직에 상당한 영향을 미쳤음을 알 수 있었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.7-12
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• 2002

반도체 공정에서 구리(Cu) 배선의 미세구조와 신뢰성에 대해 연구하였는데, 특히 CVD Cu와 전기도금 Cu를 사용하여 신뢰성에 대한 texture와 결정 구조의 영향을 연구하였다 CVD Cu의 경우 여러 가지 시드층(seed layer)을 사용함으로서, 결정입자의 크기는 비슷하지만 texture가 전혀 다른 Cu 박막을 얻을 수 있었는데, 신뢰성 검사결과 (111) texture를 가진 Cu 배선의 수명이 (200) texture를 가진 Cu 배선의 수명보다 약 4배 가량 길게 나왔다. 전기도금 Cu 박막의 경우 항상 (111) texture를 갖고 있었으며 결정립의 크기도 CVD Cu의 것보다 더 컸다. Damascene 공법으로 회로 형성한 Cu 배선의 경우에도 전기도금 Cu의 결정립 크기가 CVD Cu의 것보다 더 크게 나타났으며, 신뢰성 검사결과 배선의 수명도 더 길게 나타났는데 그 차이는 0.4 $\mu\textrm{m}$ 이하의 미세선폭 영역에서 더욱 현저했다. 따라서 전기도금 Cu가 CVD Cu보다 신뢰성 측면에서 더 우수한 것으로 판명되었다.

• Journal of the Korean Electrochemical Society
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• v.16 no.1
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• pp.19-29
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• 2013

Effects of current density, electrodeposition temperature and solution pH on properties of Cu thin films electrodeposited from pyrophosphate bath were investigated. Current efficiency was decreased with increasing current density and increased with increasing temperature. But solution pH slightly influenced on current efficiency and current efficiency was measured to be above 90% at both room temperature and $55^{\circ}C$. Residual stress of Cu thin film electrodeposited at room temperature was decreased with increasing current density, while current density reaches to 60 $mA/cm^2$ or more, stress became close to zero. Cu thin films electrodeposited at $55^{\circ}C$ exhibited the residual stress range of 0~40 MPa. At room temperature, dendritic surface morphology was observed above the current density of 30 $mA/cm^2$ and at $55^{\circ}C$, above the current density of 100 $mA/cm^2$. Cu thin films electrodeposited from bath solution with room temperature and $55^{\circ}C$ mainly consisted of (111) peaks. Specially, Cu thin film electrodeposited at 30 $mA/cm^2$ and $55^{\circ}C$ exhibited strong preferred orientation of (111) peaks.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.99-100
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• 2008

전기도금 방법은 많은 장점(낮은 증착온도, 두께 조절용이, 낮은 제조비용, 빠른 증착속도, 복잡한 형상의 물체 증착 가능 등)을 가지고 있으며 현재 FPCB의 소재인 FCCL을 제조 하는데 핵심 공정으로 많이 사용되고 있다. Sulfate 및 Pyrophosphate 용액으로부터 Cu 박막/후막을 제조 하였으며 공정 변수가 최종 도금된 Cu 박막/후막에 미치는 영향을 고찰하였다.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Journal of the Korean Electrochemical Society
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• v.3 no.2
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• pp.121-126
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• 2000

The effect of electroless Ni and Cu plating on $LaNi_5$, $AB_5$ type hydrogen storage alloy was investigated by the various electrochemical techniques such as constant current charge-discharge test, cyclic voltammeoy, and a.c. impedance spectroscopy. Scanning electron microscopy and X-ray diffraction test were conducted for phenomenological logical analyses. Cyclic Voltammetry results show that activation characteristics, cycle life and reaction ,rate were improved through electroless Ni and Cu plating. Compared with bare $LaNi_5$ the charge transfer resistance of electrode was greatly reduced as charge-discharge cycle increases. Therefore, electroless Ni and Cu plating on $LaNi_5$ alloy tends to accelerate the early activation, increasing the cyclic lift of electrode.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.142.2-142.2
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• 2007

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.137-138
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• 2011

구리 이온은 -0.40V (vs. SCE)에서 전기화학적 환원이 일어나는 반면, 니켈 이온은 -1.19V (vs. SCE)에서 전착이 발생한다. 따라서, 단일 도금욕조 내에서 Ni-Cu 합금도금층을 제조하기 위해서는 두 금속 이온종 간의 전위차를 줄여주어야 하는데, 이를 위해 본 연구에서는 $Na_3C_6H_5O_7{\cdot}2H_2O$를 착화제로 사용하였다. 다양한 Ni-Cu 합금 도금층의 조성을 얻기 위하여 기본 도금욕 내 황산니켈과 황산구리의 비율을 10:1로 설정하였다. 도금 공정 조건에 따른 합금 도금층 조성 변화를 관찰하기 위하여 도금액 pH와 교반 속도에 따른 도금층 조성 변화를 분석하였으며, 도금액의 UV-VIS과 도금층의 XRD 와 SEM 측정을 통하여 도금욕과 도금층 간의 상관 관계를 유추하였다. 본 도금액에 사용된 $Na_3C_6H_5O_7{\cdot}2H_2O$ 착화제의 효과는 pH3에서 가장 현저하였으며, pH 변화 및 교반 속도 변화를 이용하여 다양한 합금 조성을 얻을 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.117-123
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• 2014

Cu through-vias, which can be used as thermal vias or vertical interconnects, were formed using bottom-up electrodeposition filling as well as top-down electrodeposition filling into open via-holes and their microstructures were observed. Solid Cu through-vias without voids could be successfully formed by bottom-up filling as well as top-down filling with direct-current electrodeposition. While chemical-mechanical polishing (CMP) to remove the overplated Cu layer was needed on both top and bottom surfaces of the specimen processed by top-down filling method, the bottomup process has an advantage that such CMP was necessary only on the top surface of the sample.