• Corrosion Science and Technology
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• 제2권5호
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• pp.243-246
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• 2003

We have used a plasma etching method in order to develop a concave-type Pt electrode capacitor to overcome the limitation of conventional stack-type capacitor in a small critical-dimension (CD) pattern. We have deposited Pt layer on the concave-type structure made by patterning of $SiO_2$ and subsequently we separated the adjacent nodes by etch-back process with photoresist (PR) as a protecting layer.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.1269-1270
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• 2013

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.160-160
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• 2003

This paper describes some of the key issues associated with the patterning of metal electrodes of sub-micron (especially at the critical dimension (CD) of 0.15 $\mu\textrm{m}$) dynamic random access memory (DRAM) devices. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 $\mu\textrm{m}$ and thus the storage node electrode with the CD of 0.15 $\mu\textrm{m}$ could not be fabricated using the Pt electrodes. Accordingly, we have proposed novel techniques to surmount the above difficulties. The Ru electrode for the stack-type structure is introduced and alternative schemes based on the introduction of the concave-type structure using Pt or Ru as an electrode material are outlined.

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.327-331
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• 2008

An in-line wet etch/cleaning system was established for the research and development in wet etch process as a formation of electrode such as metal or transparent conductive oxide layer. A reverse moving system was equipped in the in-line wet etch/cleaning system for the alternating motion of glass substrate in a wet etch bath of the system. Therefore, it was possible for the glass substrate to be moved back and forth and it was possible to reduce the size of the system by using the reversing moving system. For the effect of the alternating motion of substrate on the etch rate in the in-line wet etch bath, indium tin oxide(ITO) patterns were obtained through wet etch process in the in-line system in which the substrate was moved back and forth. From the CD(critical dimension) skews resulted from the ADI CD and ACI CD of the ITO patterns, it was concluded that the alternating motion of glass substrate are possible to be applied to the mass production of wet etch process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.39-42
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• 2000

As gate dimensions continue to shrink below $0.2{\mu}m$, improving CD (Critical Dimension) control has become a major challenge during CMOS process development. Anti-Reflective Coatings are widely used to overcome high substrate reflectivity at Deep UV wavelengths by canceling out these reflections. In this study, we have investigated Batchtype system for PECVO SiOxNy as Anti-Reflective Coatings. The Singletype system was baseline and Batchtype system was new process. The test structure of Singletype is SiON $250{\AA}$ + Cap Oxide $50{\AA}$ and Batchtype is SiON $250{\AA}$ + Cap Oxide $50{\AA}$ or N2O plasma treatment. Inorganic chemical vapor deposition SiOxNy layer has been qualified for bottom ARC on Poly+WSix layer, But, this test was practiced on the actual device structure of TiN/Al-Cu/TiN/Ti stacks. A former day, in Batchtype chamber thin oxide thickness control was difficult. In this test, Batchtype system is consist of six deposition station, and demanded 6th station plasma treatment kits for N2O treatment or Cap Oxide after SiON $250{\AA}$. Good reflectivity can be obtained by Cap Oxide rather than N2O plasma treatment and both system of PECVD SiOxNy ARC have good electrical properties.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Journal of the Optical Society of Korea
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• 제16권3호
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• pp.221-227
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• 2012

We propose optical proximity corrections (OPCs) for digital micromirror device (DMD)-based maskless lithography. A pattern writing scheme is analyzed and a theoretical model for obtaining the dose distribution profile and resulting structure is derived. By using simulation based on this model we were able to reduce the edge placement error (EPE) between the design width and the critical dimension (CD) of a fabricated photoresist, which enables improvement of the CD. Moreover, by experiments carried out with the parameter derived from the writing scheme, we minimized the corner-rounding effect by controlling light transmission to the corners of a feature by modulating a DMD.

• 한국정밀공학회지
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• 제21권6호
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• pp.7-14
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• 2004

나노 임프린트 기술은 기존의 광학적 리소그라피 (optical lithography) 기술보다 저렴한 비용으로 나노 구조물을 대량으로 제조할 수 있을 것으로 기대되고 있는 기술이다. 현재까지 반도체 공정기술의 주류를 이루고 있는 광학적인 리소그라피 기술은, 100nm이상의 CD(Critical Dimension)를 가지는 구조물들을 정밀하게 제조하여, 미소전자공학 (microelectronics) 소자, MEMS/MEMS, 광학소자 등의 제품들을 대량으로 생산하는 데에 널리 활용되고 있다. 반도체 소자의 고집적화 경향에 따라 100 nm 이하의 CD를 가지는 나노 구조물들을 제조할 필요성이 높아지고 있지만, 광학적인 방법으로는 광원의 파장보다 작은 구조물들을 제조하기가 어렵다. 보다 짧은 파장을 가지는 광원을 이용하는 리소그라피 장비가 계속적으로 개발되고 있으나, 그에 따른 장비 비용 및 제조 단가가 기하급수적으로 증가하고 있다.(중략)

• 제어로봇시스템학회논문지
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• 제4권4호
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• pp.506-516
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• 1998

In this paper, an algorithm is proposed to detect the malfunction of plasma-etching characteristics using EPD signal trajectories. EPD signal trajectories offer many information on plasma-etching process state, so they must be considered as the most important data sets to predict the wafer states in plasma-etching process. A recent work has shown that EPD signal trajectories were successfully incorporated into process modeling through critical parameter extraction, but this method consumes much effort and time. So Principal component analysis(PCA) can be applied. PCA is the linear transformation algorithm which converts correlated high-dimensional data sets to uncorrelated low-dimensional data sets. Based on this reason neural network model can improve its performance and convergence speed when it uses the features which are extracted from raw EPD signals by PCA. Wafer-state variables, Critical Dimension(CD) and uniformity can be estimated by simulation using neural network model into which EPD signals are incorporated. After CD and uniformity values are predicted, proposed algorithm determines whether malfunction values are produced or not. If malfunction values arise, the etching process is stopped immediately. As a result, through simulation, we can keep the abnormal state of etching process from propagating into the next run. All the procedures of this algorithm can be performed on-line, i.e. wafer to wafer.