• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.39-44
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• 2003

As the portable electronic equipments are developed and popularized, the batteies are more important. To prolong life of the equipments, engineers demand to have batteries of high-power density and they are used to use Li-ion batteries popularly Li-ion batteries are better than conventional batteries, Ni-cd, about power density per volume and weight, but they have a fault that discharge voltage of them goes down. In order to maximize life of the Li-ion batterries, we have to use a converter which is suitable for the characteristic of Li-ion batteries. Therefore, capacitive idling SEPIC(Single Ended Primary Inductance Converter) that is derived from the SEPIC topology is proposed as a source of the Portable low-power applications. The converter has characteristics of buck-boost porformance. Besides, that makes it possible to increase the switching frequency by partial soft commutation of power switches through adding a diode and a switch. This paper is presented the characteristics, DC voltage conversion ratio, circuits of operation modes, of the converter and it is analized and implemented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• Journal of Power Electronics
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• v.19 no.4
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• pp.881-893
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• 2019

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

• Journal of IKEEE
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• v.24 no.4
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• pp.1074-1080
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• 2020

This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.4975-4983
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• 2010

In this paper, the ordinariest and strongest simulator that many used to power electronics circuits and many different control technology can apply to more easily understand modeling the element, PSPICE and MATLAB are adapted a micro IGBT, a macro IGBT, PWM generator and to library moeling of validity of the Induction motor is interpreted. Micro IGBT model of demagnetization quality proved for modeling accuracy to through experiment, macromodel IGBT were simulated which the applied to voltage type PWM inverter to the cyclo-converter and induction motor of demagnetization.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.25-30
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• 2014

This paper describes the design of gate driver circuits in distributed maximum power point tracking(DMPPT) controller for photovoltaic system. For the effective DMPPT control in the existence of shadowed modules, high voltage gate driver is applied to drive the DC-DC converter in each module. Some analog blocks such as 12-b ADC, PLL, and gate driver are integrated in the SoC for DMPPT. To reduce the power consumption and to avoid the high voltage damage, a short pulse generator is added in the high side level shifter. The circuit was implemented with BCDMOS 0.35um technology and can support the maximum current of 2A and the maximum voltage of 50V.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.221-225
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• 2014

Low power RF devices, such as RFID and Zigbee, are important for ubiquitous sensing. These devices, however, are powered by portable energy sources, such as batteries, which limits their use. To mitigate this problem, this study developed RF energy harvesting with W-CDMA for a low power RF device. Diodes are required with a low turn on voltage because the diode threshold is larger than the received peak voltage of the rectifying antenna (rectenna). Therefore, a Schottky diode HSMS-286 was used. A prototype of RF energy harvesting device showed the maximum gain of 5.8dBi for the W-CDMA signal. The 16 patch antennas were manufactured with a 10 dielectric constant PTFT board. In low power RF devices, the transmitter requires a step-up voltage of 2.5~5V with up to 35 mA. To meet this requirement, the Texas Instruments TPS61220 was used as a low input voltage step-up converter. From the evaluated result, the achievable incident power of the rectenna at 926mV to operate Zigbee can be obtained within a distance of 12m.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.89-96
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• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gain control are proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0㎃ to 300㎃ over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than 1.4% over the current range from 0A to 300㎃.