• 한국컴퓨터그래픽스학회논문지
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• 제6권3호
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• pp.1-7
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• 2000

래스터 그래픽스 시스템에서 처리되는 픽슬의 수는 한 프래임 당 100 만 개가 넘을 경우가 많다. 따라서, 그래픽스 프리미티브를 랜더링에서 실수연산을 정수연산으로 대체 함으로써 많은 처리속도 향상이 된다. 본 논문에서는, 스케일링에 의하여 그래픽스 프리미티브 랜더링 알고리즘의 실수연산을 정수연산으로 대체하는 방법을 소개한다. 이 방법은 필터링 된 직선 그리기와 구로세이딩에 적용된다. 또한, 이 방법은 증가적 방법에 근거한 다른 그래픽스 랜더링 알고리즘에도 적용 될 수 있다. 특히, 이 방법은 이미 ASIC 구현이 된 기존의 알고리즘에서 극히 일부분의 단순 수정을 요구하기 때문에 ASIC 구현이 용이하다.

• Kyungpook Mathematical Journal
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• 제54권4호
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• pp.521-529
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• 2014

In this paper we derive some optimal convex combination bounds related to arithmetic mean. We find the greatest values ${\alpha}_1$ and ${\alpha}_2$ and the least values ${\beta}_1$ and ${\beta}_2$ such that the double inequalities $${\alpha}_1T(a,b)+(1-{\alpha}_1)H(a,b)<A(a,b)<{\beta}_1T(a,b)+(1-{\beta}_1)H(a,b)$$ and $${\alpha}_2T(a,b)+(1-{\alpha}_2)G(a,b)<A(a,b)<{\beta}_2T(a,b)+(1-{\beta}_2)G(a,b)$$ holds for all a,b > 0 with $a{\neq}b$. Here T(a,b), H(a,b), A(a,b) and G(a,b) denote the second Seiffert, harmonic, arithmetic and geometric means of two positive numbers a and b, respectively.

• 한국멀티미디어학회논문지
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• 제11권6호
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• pp.816-827
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• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.715-718
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• 2005

Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

• 한국정보보호학회:학술대회논문집
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• 한국정보보호학회 1998년도 종합학술발표회논문집
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• pp.537-545
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• 1998

This paper is the research about a joint coding system of source and channel coding using VF(Variable-to-fixed length) arithmetic code and BCH code. We propose a VF arithmetic coding method with EDC( Error Detecting Capability) and a joint coding method in that the VF arithmetic coding method with EDC is combined with BCH code. By combining both the VF arithmetic code with EDC and BCH code. the proposed joint coding method corrects a source codeword with t-errors in decoding of BCH code and carries out a improvement of the EDC of a codeword with more than (t＋1)-errors in decoding of the VF arithmetic coding with EDC. We examine the performance of the proposed method in terms of compression ratio and EDC.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.145-149
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• 2015

A reconfigurable lighting engine for widely used lighting models is proposed for low-power GPU shaders. Conventionally, lighting operations that involve many complex arithmetic operations were calculated by the shader programs on the GPU, which led to a significant energy overhead. In this letter, we propose a lighting engine to improve the energy-efficiency by supporting the widely used advanced lighting models in hardware. It supports the Blinn-Phong, Oren-Nayar, and Cook-Torrance models, by exploiting the logarithmic arithmetic and optimizing the trigonometric function evaluations for the energy-efficiency. Experimental results demonstrate 12.7%, 42.5%, and 35.5% reductions in terms of power-delay product from the shader program implementations for each lighting model. Moreover, our work shows 10.1% higher energy-efficiency for the Blinn-Phong model compared to the prior art.

• 한국수학교육학회지시리즈D:수학교육연구
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• 제18권1호
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• pp.31-40
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• 2014

Working with dynamic visual representations can help students-with-computer discover new mathematical ideas. Students translate among multiple representations as a strategy to investigate non-routine problems to explore possible solutions in mathematics classrooms. In this paper, we use the area models as new representations for our secondary students to investigate three problems related to the average speed of a particle. Students show their ideas in the process of investigating arithmetic mean, harmonic mean, and average speed through their created dynamic figures. These figures really utilize dynamic geometry software.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1986년도 춘계학술발표회 논문집
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• pp.177-180
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• 1986

A high performance Butterfly Arithmetic Unit for FFT processor using two adders is proposed in this papers, which is Based on the distributed and merged arithmetic. Due to simple and easy architecture to implement, this proposed processor is well suited to systolic FFT processor. Simulation was performance using YSLOG (Yonsei logic simulator) on IBM AT computer, to verify logic. By using 3um double Metal CMOS technology,Butterfly arithmetic have been achieved in 1.2 usec.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• 한국수학사학회지
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• 제12권2호
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• pp.47-54
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• 1999

We introduce some historical facts on number theory, especially prime numbers and modular arithmetic. And then, with the viewpoint of computer arithmetic, residue number systems are considered as an alternate to positional number systems so that high performance and high speed computation can be achieved in a specified domain such as cryptography and digital signal processing.