• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.4
• /
• pp.307-311
• /
• 2004

This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in $GF(2^8)$ to composite field $GF(((2^2)^2)^2)$ where more efficient computations can be implemented and transform the computed result back to $GF(2^8)$. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.

• KIPS Transactions on Computer and Communication Systems
• /
• v.8 no.11
• /
• pp.271-276
• /
• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.8
• /
• pp.67-74
• /
• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.4
• /
• pp.1-6
• /
• 2020

This paper proposes the design of an advanced S-Box for calculating multiplicative inverse in AES encryption process. In this approach, advanced S-box module is first designed based on composite field, and then the performance evaluation is performed for S-box with multi-stage pipelining architecture. In the proposed S-Box architecture, each module for multiplicative inverse is constructed using combinational logic for realizing both small-area and high-speed. Through logic synthesis result, the designed 3-stage pipelined S-Box shows speed improvement of about 28% compared to the conventional method. The proposed advanced AES S-Box is performed modelling at the mixed level using Verilog-HDL, and logic synthesis is also performed on Spartan 3s1500l FPGA using Xilinx ISE 14.7 tool.

• ETRI Journal
• /
• v.30 no.5
• /
• pp.707-717
• /
• 2008

This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over $GF(2^4)^2$, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 ${\mu}m$ CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.19 no.4
• /
• pp.21-28
• /
• 2009

In the recent years, power attacks were widely investigated, and so various countermeasures have been proposed, In the case of block ciphers, masking methods that blind the intermediate values in the algorithm computations(encryption, decryption, and key-schedule) are well-known among these countermeasures. But the cost of non-linear part is extremely high in the masking method of block cipher, and so the inversion of S-box is the most significant part in the case of AES. This fact make various countermeasures be proposed for reducing the cost of masking inversion and Zakeri's method using normal bases over the composite field is known to be most efficient algorithm among these masking method. We rearrange the masking inversion operation over the composite field and so can find duplicated multiplications. Because of these duplicated multiplications, our method can reduce about 10.5% gates in comparison with Zakeri's method.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.22 no.1
• /
• pp.1-6
• /
• 2022

In this paper, the design of lightweight S-Box structure for implementing a low power AES cryptosystem based on composite field. In this approach, the S-Box is designed as a simple structure by which the three modules of x², λ, and GF((2²)²) merge into one module for improving the usable area and processing speed on GF(((2²)²)²). The designed AES S-Box is modelled in Veilog-HDL at structural level, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool, where Spartan 3s1500l is used as a target FPGA device. It is shown that the designed S-Box is correctly operated through simulation result, where ModelSim 10.3. is used for performing timing simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.2
• /
• pp.1-6
• /
• 2021

In this paper, an efficient implementation of AES encryption algorithm is presented for CCTV image security using C# language. In this approach, an efficient S-Box is first designed for reducing the computation time which is required in each round process of AES algorithm, and then an CCTV image security system is implemented on the basis of this algorithm on a composite field GF(((22)2)2). In addition, the shared S-Box structure is designed for realizing the minimized memory space, which is used in each round transformation and key scheduling processes. Through performance evaluation, it was confirmed that the proposed method is more efficient than the existing method. The proposed CCTV system in C# language using Visual studio 2010.

• Proceedings of the Korean Society For Composite Materials Conference
• /
• 2004.04a
• /
• pp.13-17
• /
• 2004

In recent years, the deterioration of reinforced concrete structures has become a serious problem in civil engineering fields. This situation is mainly due to corrosion of steel reinforcing bars embedded in concrete. Recently, there has been a greatly increased demand for the use of FRP (fiber reinforced plastic) in civil engineering field due to their superior mechanical and physical properties. This paper presents an experimental study on the behavior of concrete bridge deck reinforced with FRP Box, FRP Plate, and FRP Re-bar. In tlIe study, mechanical properties of FRP Box, FRP Plate, GFRP Re-bar, and CFRP Grid have been investigated. Full scale one-way deck slab was tested under four point lateral load (equivalent to actual wheel load of DB-24 including impact). Load-deflection and load-strain data were collected through LVDT's and strain gages attached to the specimen.

• Steel and Composite Structures
• /
• v.17 no.3
• /
• pp.237-252
• /
• 2014

The use of composite structures is increasingly present in civil building works. Composite Box Girder Bridges (CBGB), particularly, are study of effect of shear connector's numbers and distribution on the behavior of CBGBs is submitted. A Predicti structures consisting of two materials, both connected by metal devices known as shear connectors. The main functions of these connectors are to allow for the joint behavior of the girder-deck, to restrict longitudinal slipping and uplifting at the element's interface and to take shear forces. This paper presents 3D numerical models of CBGBs to simulate their actual structural behavior, with emphasis on the girder-deck interface. Additionally, a Prediction of several FE models is assessed against the results acquired from a field test. A number of factors are considered, and confirmed through experiments, especially full shear connections, which are obviously essential in composite box girder. A good representation for shear connectors by suitable element type is considered. Numerical predictions of vertical displacements at critical sections fit fairly well with those evaluated experimentally. The agreement between the FE models and the experimental models show that the FE model can aid engineers in design practices of box girder bridges. Preliminary results indicate that number of shear studs can be significantly reduced to facilitate adoption of a new arrangement in modeling CBGBs with full composition. However, a further feasibility study to investigate the practical and economic aspects of such a remedy is recommended, and it may represent partial composition in such modeling.