• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.2
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• pp.113-118
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• 2005

This paper shows a satellite battery cell voltage monitor system to make differential voltage measurements when one or both measurement points are beyond voltage range allowed by a conventional differential amplifier. This system is particularly useful for monitoring the individual cell voltage of series-connected cells that constitute a rechargeable satellite battery in which some cell voltages must be measured in the presence of high common mode voltage.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.186-190
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• 2000

This paper propose a "Active common-mode voltage damper circuit" that capable of a suppression of a common-mode voltage produced in the PWM VSI. The four level half-bridge PWM inverter circuit and common-mode transformer are incorporated into the "Active common-mode voltage damper" the design method of which is presented Effect of "Active common-mode voltage damper" in this paper verifies a propriety and effectiveness in 2.2[kW] induction motor drive using IGBT inverter. Experimental results show that "common-mode voltage damper" makes contributions to reducing a high frequency leakage current and common-mode voltage.leakage current and common-mode voltage.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.151-154
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• 2001

This paper propose a new active common-mode voltage damper circuit that is capable of suppressing a common-mode voltage produced in the PWM VSI. The new active common mode voltage damper is consisted of a half-bridge inverter and a common mode transformer with a blocking capacitor. Principle of the active common mode damper is as follow; by applying the compensation voltage which has the same amplitude and opposite polarity to the PWM inverter system. So, common mode voltage and high frequency leakage current can be reduced. Simulated and experimental results show that common-mode voltage damper makes contributions to reducing a high frequency leakage current and common-mode voltage.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.311-312
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• 2015

본 논문에서는 Unipolar PWM 스위칭 (Totem pole) 방법을 사용하는 단상인버터에서 나타나는 common mode noise를 저감시키는 스위칭 방법을 제안한다. 제안하는 방법은 출력전압의 중성점(N)을 입력전압 양단에 항상 고정하도록 스위칭을 하여 Common Mode Noise를 저감했다. 이를 Matlab Simulink를 사용한 모의해석과 실험을 통하여 Noise의 원인과 효과를 입증하였다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.287-288
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• 2014

본 논문에서는 3레벨 4레그 컨버터에서 커먼 모드 전압(Common-mode Voltage, CMV)을 저감하기 위한 삼각파 비교 전압 변조 기법을 제안하였다. 제안한 PWM 방법은 매우 직관적이고, DSP 제어 시스템에서 쉽게 구현할 수 있다. SVPWM, SPWM의 스위칭 패턴 분석을 통하여 CMV 저감을 위한 4번째 레그(f상)의 극 전압 패턴을 제안하였고, 해당하는 f상 극 전압의 합성을 위하여, f상 양/음의 극 전압 지령 값을 계산하였다. 또한 a, b, c상 전압 왜곡을 막기 위한 옵셋 전압을 유도하였다. 제안한 PWM 방법의 유효성은 모의실험과 실험 결과를 통하여 검증되었다. 제안된 방법에서 CMV의 첨두치 및 스위칭 수는 SVPWM 방법에 비하여 각각 33%, 25%로 대폭 감소하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.81-88
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• 2006

This paper describes a new linear operational transconductance amplifier (OTA). To improve the linearity of the OTA, we employ a mobility compensation circuit that combines the transistor paths operating at the triode and subthreshold regions. The common-mode control schemes consist of a common-mode feedback (CMFB) and common-mode feedforward (CMFF). The circuit enhances linearity of the transconductance (Gm) under the wide input voltage swing range. The proposed OTA shows ${\pm}1%$ Gm variation and the total harmonic distortion (THD) of below -73dB under the input voltage swing range of ${\pm}1.1V$. The OTA is implemented using a $0.35{\mu}m$ n-well CMOS process under 3.3V supply.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.73-74
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• 2017

본 논문에서는 H7 인버터와 DPWM 기반의 개선된 변조 기법을 이용한 2-레벨 인버터의 커먼 모드(Common Mode) 전압 저감 방법을 제안한다. 기존의 H7 인버터를 이용한 커먼 모드 전압 저감 방법은 스위칭 신호 구현을 위해 추가적인 논리회로가 필요하고, 일부 영역에서 커먼 모드 전압 저감이 이루어지지 않는 문제점이 있다. 제안하는 방법은 옵셋(Offset) 전압을 이용한 변조 방식을 사용하여 3상 인버터의 스위칭 신호를 생성하고, 3상의 지령 값을 이용하여 7번째 스위치의 스위칭 패턴을 결정한다. 이를 통해 추가적인 논리 회로 없이 하나의 캐리어만을 이용하여 모든 스위치의 스위칭 신호를 구현하며, 모든 영역에서 커먼 모드 전압 저감이 이루어지도록 하였다. 제안된 방법의 커먼 모드 전압 저감, 출력 상전류 왜곡 특성에 대한 성능을 시뮬레이션을 통해 검증하였다.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1515-1517
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• 2005

In this paper, we represent both occurrence reason of Surge-voltage and Leakage-current of AC drive system which is operated by Voltage-type PWM Inverter. It generates a compensating voltage which has the same amplitude as, but the opposite phase to, the common-mode voltage produced by the PWM inverter. The compensating voltage is superimposed on the inverter output by a common-mode transformer. As a result, the common-mode voltage applied to the load is canceled completely. The design method of the active common-mode noise canceler is also presented in detail. Therefore, we try to describe the method controling both of them and all of the proprieties are proved by our experiment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.867-880
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• 1992

In this paper, a circuit design techniques for Improving the voltage gain of the GaAs MESFET single amplifier is presented. Also, various types of existing current mirror and proposed current mirror of new configuration are compared. To obtain the high differential mode gain and low common mode gain, bootstrap gain enhancement technique Is used and common mode feedback Is employed In the design of differential amplifier. The simulation results show that designed differential amplifier has differential gain of 57.66dB, unity gain frequency of 23.25GHz. Also, differential amplifier using common mode feedback with alternative negative current mirror has CMRR of 83.S8dB, stew rate of 3500 V /\ulcorners.