• 전자공학회논문지B
• /
• 제32B권11호
• /
• pp.1374-1382
• /
• 1995

In TFT-LCDs, as the display size area becomes larger, and the resolution higher, we have to consider the image degradation effects due to the incorporation of the TFT-LCD parameters such as the data-line resistance, the common electrode resistance, the data-line to common parasitic capacitance, and the output characteristics of driver ICs. One of the degradation effects is crosstalk resulting from the coupling between the source bus-line and common electrode. Since a source signal which represents a large number of display data is supposed to vary frequently, the common signal level is affected through the coupling effect, resulting in the degradation of nearby pixel drive signals. Therefore, we proposed a method to compensate for this source-common electrode coupling effect, we also designed and experimented the feasibility of our crosstalk compensation circuit in the actual TFT-LCD. We saw that the newly designed compensation circuit greatly reduced the crosstalk in display pattern image.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2004년도 ICCAS
• /
• pp.493-498
• /
• 2004

The EMI noise source in a switching mode power supply is dominated by a common mode noise. If we can understand the common mode noise occurring mechanism, it is resulted to find out the method to suppress the EMI noise source in the switching mode power supply. The common mode noise is occurring mostly due to circuit is unbalanced which is caused by the capacitive coupling to frame ground, which passes through a heatsink of the switching devices. This research paper presents a new effective balancing method of buck converter circuit by mean of grounding the parasitic and compensation capacitors in correct proportion which is called that the common mode impedance balance (CMIB). The CMIB can be achieved by source, transmission line and termination balanced, such balancing, the common mode current will be cancelled out in the frame ground. The greatly reduced common mode noise can be confirmed by the experimental results.

• Transactions on Electrical and Electronic Materials
• /
• 제7권4호
• /
• pp.180-183
• /
• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• Journal of Power Electronics
• /
• 제18권1호
• /
• pp.81-91
• /
• 2018

This paper proposes a double line voltage synthesis (DLVS) strategy for three-to-five phase direct matrix converters. In the proposed strategy, the input and expected output voltages are divided into 6 segments and 10 segments, respectively. In addition, in order to obtain the maximum voltage transfer ratio (VTR), the input line voltages and "source key" should be selected reasonably according to different combinations of input and output segments. Then, the corresponding duty ratios are calculated to determine the switch sequences in different segment combinations. The output voltages and currents are still sinusoidal and symmetrical with little lower order harmonics under unbalanced or distorted input voltages by using this strategy. In addition, the common mode voltage (CMV) can be suppressed by rearranging some of the switching states. This strategy is analyzed and studied by a simulation model established in MATLAB/Simulink and an experimental platform, which is controlled by a DSP and FPGA. Simulation and experimental results verify the feasibility and validity of the proposed DLVS strategy.

• 한국전기전자재료학회논문지
• /
• 제18권3호
• /
• pp.193-198
• /
• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 하계학술대회 논문집
• /
• pp.26-31
• /
• 2002

To realize a high integrated Flash memory utilizing SONOS memory devices, the NOR type 1TC(one Transistor Cell) SONOS Flash arrays are fabricated and characterized. This SONOS Flash arrays with common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cell is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$. To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and Bit line erase method are selected as the write operation and the erase method, respectively. The disturbance characteristics according to the write/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• 한국전기전자재료학회논문지
• /
• 제16권5호
• /
• pp.372-377
• /
• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

• 대한전자공학회논문지TC
• /
• 제47권10호
• /
• pp.74-79
• /
• 2010

본 논문에서는 70 nm mHEMT MMIC 기술을 이용한 고이득 W-band 증폭기를 제시한다. W-band에서 고이득 특성을 얻기 위하여 공통 소스 FET의 소스 피드백 라인의 길이를 조절하면 설계 주파수에서 이득이 최대가 되도록 하였다. 이 라인의 길이를 조절하여 94 GHz에서 MAG를 0.8 dB 향상 시킬 수 있음을 시뮬레이션에서 확인하였다. 뿐만 아니라, 이 소스 피드백 라인은 FET의 입력 임피던스도 변화시켜 입력 정합을 용이하게 한다. 이 현상을 이용하여 공통 소스 FET 4단으로 이루어진 w-band 증폭기를 CPW로 설계하였다. 제작된 W-band 증폭기는 측정 결과 70~103 GHz에서 22.0 dB 이상의 아주 우수한 이득 특성을 보였다.

• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2008년도 춘계학술대회 논문집
• /
• pp.332-338
• /
• 2008

This paper handles, implementation of multiple access bidirectional serial communications protocol using two common DC power lines, whict are power supply and ground, connecting multiple devices. Communication between the host and the multiple clients are performed using unique packet data with device ID unique to each devices connected on the common power lines. Host initiates data communications by transmitting command packet to the designated client with the client's ID and the client responds by transmitting response packet to the host and in this way, multiple clients and host exchange the packet through the common power lines. The normal voltage of the power communication line maintains 24V corresponding to level 1 and the host drops the voltage to 12V on sending level 0 signal, also the clients normally keeps the line voltage to 24V use pull-down circuit to drop the voltage to 12V on sending level 1 signal. Power supply originates from the host, the host senses the voltage level of the power communication lines and when the clients activates pull down circuit to send level 0 signal and the voltage drops to 12V, the hosts switches power source from 24V to 12V. Also, when clients deactivate pull down circuit to send level 1 signal, the host senses the voltage increase and switches the power source from 12V to 24V. Experimental circuit is designed with one hosts and four clients and verified the power line voltage switching operation depending on the data signal levels on the power line. The proposed research result can be applied to two wire power communications system with one host and multiple low current consumption clients.

• 전력전자학회논문지
• /
• 제27권2호
• /
• pp.92-99
• /
• 2022

Due to space and geographical constraints, the power source may be located outside the island area, resulting in the considerable length of transmission line. In these cases, when an active power is transmitted, unexpected reactive power is generated at a point of common coupling (PCC). Unlike the power transmitted from the power generation source, the reactive power adversely affects the system. This study proposes a new algorithm that controls reactive power at PCC. Causes of reactive power errors are separated into parallel and series components, which allows the algorithm to compensate the reactive current of the inverter output and control reactive power at the PCC through calculations from the impedance, voltage, and current. The proposed algorithm has economic advantages by controlling the reactive power with the inverter of the power source itself, and can flexibly control power against voltage and output variations. Through the simulation, the algorithm was verified by implementing a power source of 3 [kVA] capacity connected to the low voltage system and of 5 [MVA] capacity connected to the extra-high voltage system. Furthermore, a power source of 3 [kVA] capacity inverter is configured and connected to a mock grid, then confirmed through experiments.