• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.7
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• pp.557-562
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• 2000

160nm thick amorphous Si and polycrystalline Si were each deposited on to 10nm thick SiO$_2$, Co monolayer and Co/Ti bilayer were sequentially evaporated to form Co-polycide. Then MOS capacitors were fabricated by BF$_2$ ion-implantation. The characteristics of the fabricated capacitor samples depending upon the drive-in annel conductions were measured to study the effects of thermal stability of CoSi$_2$and dopant redistribution on electrical properties of Co-polycide gates. Results for capacitors using Co/Ti bilayer and drive-in annealed at 80$0^{\circ}C$ for 20~40sec. showed excellent C-V characteristics of gate electrode.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.77.2-77
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• 1998

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1117-1122
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• 1999

Amorphous Si and Co/Ti bilayers were sequentially evaporated onto 5- 10nm thick $\textrm{CoSi}_{2}$ and rapidly thermal-annealed(RTA) to form Co-polycide electrodes. Then, MOS capacitors were fabricated by doping poly-Si using SADS method. The C-V and leakage-current characteristics of the capacitors depending upon the RTA conditions were measured to study the effects of thermal stability of $\textrm{CoSi}_{2}$ and dopant redistribution on electrical properties of Co -polycide gates. Capacitors RTAed at $700^{\circ}C$ for 60-80 sec., showed excellent C-V and leakage-current characteristics due to degenate doping of poly-Si layers. But for longer time or at higher temperature, their electrical properties were degraeded due to $\textrm{CoSi}_{2}$ decomposition and subsequent Co diffusion. When making Co-polycide gate electrodes by SADS, not only degenerate doping of poly-Si layer. but also suppression of have been shown to be very critical.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.332-337
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• 2006

We prepared 100 nm-thick CoNi composite silicide on a 70 nm-thick polysilicon substrate. Composite silicide laye.s were formed by rapid thermal annealing(RTA) at the temperatures of $700^{\circ}C,\;900^{\circ}C,\;1000^{\circ}C$ for 40 seconds. A Focused ion beam (FIB) was used to make nano-patterns with the operation range of 30 kV and $1{\sim}100$ pA. We investigated the change of thickness, line width, and the slope angle of the silicide patterns by FIB. More easily made with the FIB process than with the conventional polycide process. We successfully fabricated sub-100nm etched patterns with FIB condition of 30kv-30pA. Our result implies that we may integrate nano patterns with our newly proposed CoNi composite silicides.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.473-476
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• 1999

PMOS capacitors with Ce-policide electrode were fabricated by the SADS method to study the effects of activation condition on the C-V characteristics. For the activation temperature of $600^{\circ}C$ , the capacitor using CoSi$_2$ formed from Co/Ti bilayer as diffusion source showed excellent C-V properties and the increase in V$_{th}$ with the increasing activation time. But impurties into the oxide.e.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1581-1584
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• 2008

In dual-polycide-gate structure with butting contact, net doping concentration of polysilicon was decreased due to overlap between $n^+$ and $p^+$ and lateral dopant diffusion in silicide/polysilicon layers. The generation of parasitic Schottky diode in butting contact region is attributed both to the $CoSi_2$-loss due to $CoSi_2$ agglomeration and to the decrease in net doping concentration of polysilicon layer. Parasitic Schottky diode reduces noise margin of sense amplifier in DDI DRAM, which causes column fail. The column fail could be reduced by physical isolation of $n^+/p^+$ polysilicon junction or suppressing $CoSi_2$ agglomeration by using nitrogen implantation into $p^+$ polysilicon before $CoSi_2$ formation.

• Korean Journal of Materials Research
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• v.8 no.6
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• pp.499-504
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• 1998

For the formation of cobalt polycide gate electrode, CoSi, was grown on columnar poly-Si, granular poly-Si or amorphous Si by depositing either Co monolayer or Co/Ti bilayer and its thermal stability was compared to study effects of the substrate crystallinity and the silicide formation method. When specimens were rapidly heat-treated at 90$0^{\circ}C$ up to 600 seconds, using amorphous Si or Co/Ti on all substrates improved the thermal stability. This was attributed to the uniform chemical composition of initial CoSi, and its smooth interface with the substrates, induced by smooth and clean Si surface and delayed Co diffusion. The main factors determining the thermal stability were found to be composition uniformity and smooth interface of $CoSi_2$, intially formed at the early stage of the heat-treatment.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.266-269
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• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Korean Journal of Materials Research
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• v.13 no.1
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• pp.1-5
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• 2003

Uniform polycrystalline $CoSi_2$layers have been grown in situ on a polycrystalline Si substrate at temperature near $625^{\circ}C$ by reactive chemical vapor deposition of cyclopentadienyl dicarbonyl cobalt, Co(η$^{5}$ -C$_{5}$ H$_{5}$ )(CO)$_2$. The growth behavior and thermal stability of $CoSi_2$layer grown on polycrystalline Si substrates were investigated. The plate-like CoSi$_2$was initially formed with either (111), (220) or (311) interface on polycrystalline Si substrate. As deposition time was increasing, a uniform epitaxial $CoSi_2$layer was grown from the discrete $CoSi_2$plate, where the orientation of the$ CoSi_2$layer is same as the orientation of polycrystalline Si grain. The interface between $CoSi_2$layer and polycrystalline Si substrate was always (111) coherent. The growth of the uniform $CoSi_2$layer had a parabolic relationship with the deposition time. Therefore we confirmed that the growth of $CoSi_2$layer was controlled by diffusion of cobalt. The thermal stability of $CoSi_2$layer on small grain-sized polycrystalline Si substrate has been investigated using sheet resistance measurement at temperature from $600^{\circ}C$ to $900^{\circ}C$. The $CoSi_2$layer was degraded at $900^{\circ}C$. Inserting a TiN interlayer between polycrystalline Si and $_CoSi2$layers improved the thermal stability of $CoSi_2$layer up to $900^{\circ}C$ due to the suppression of the Co diffusion.