• Journal of the Optical Society of Korea
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• v.16 no.3
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• pp.215-220
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• 2012

In an earlier work, we proposed the chromatic dispersion monitoring technique of non-return to zero (NRZ) signal based on clock-frequency component (CFC) through numerical simulations. However, we have not yet shown any experimental demonstration or analytic derivation of it. In this paper, we show an experimental demonstration and analytic derivation of the proposed chromatic dispersion monitoring technique. We confirm that the experimental results and the analytic results correspond with the simulation results. We also demonstrate that monitoring range and accuracy can be improved by using a simple clock-extraction method.

• ETRI Journal
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• v.30 no.3
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• pp.461-468
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• 2008

This paper presents a chromatic dispersion monitoring technique using a clock-frequency component for carrier-suppressed return-to-zero (CSRZ) signal. The clock-frequency component is extracted by a clock-extraction (CE) process. To discover which CE methods are most efficient for dispersion monitoring, we evaluate the monitoring performance of each extracted clock signal. We also evaluate the monitoring ability to detect the optimum amount of dispersion compensation when optical nonlinearity exists, since it is more important in nonlinear transmission systems. We demonstrate efficient CE methods of CSRZ signal to monitor chromatic dispersion for optimum compensation in high-speed optical communication systems.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.9
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• pp.1343-1349
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• 2013

In optical fiber communications, several newly-developed signal formats are used to obtain the best performance within limited spectral bandwidth. CSRZ (carrier-suppressed return-to-zero) format is one of the new signal formats, which has better spectral efficiency and better robustness to dispersion than RZ (return-to-zero) format. Thus it is widely used for demonstrating high-speed optical communication systems. In an earlier research, we proposed a clock-extraction method of CSRZ signal to monitor chromatic dispersion. However, the clock-frequency component extracted by the clock-extraction method can be affected by the bandwidth of a transmitter or a receiver. Therefore, in this paper, we investigate the effect of bandwidth on the chromatic dispersion monitoring of CSRZ signal based on clock-frequency component. As a result, we propose a couple of robust clock-extraction methods to monitor chromatic dispersion in CSRZ signal.

• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.330-334
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• 2000

A new pha~e lock loop (PLL) IS proposed and demonstrated fat clock recovery from 40 Gblt/s time-dIvision-multiplexed (TDM) optical pulse tri.lin, The proposed clock lecovery scheme lmproves the Jitter effecl cOlmng from the clock. pulse laser of harmonically-mode locked flber laser The cross-corrdation frequency component between the optical Signa] and an optical clock pulse tram is deteCled as a fonr-wave-mixing (FWM) SIgnal generated in SOA. The lock-in freqnency range of the clod. recovery IS found to be within 10 KHz. 0 KHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• Journal of Korea Multimedia Society
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• v.8 no.10
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• pp.1403-1410
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• 2005

The synchronization problem is directly related to the quality of service in multimedia communication and especially in real-time communication. In this study, we found the cause of clock fluctuation between encoder and decoder in MPEG-2 system layer was that the standard decoder design only considered a fixed time delay component. To solve it, we proposed Extended-SRTS algorithm, which uses STC as service clock by synchronizing transport stream. As the result, we can improve the effect of frequency-drift, time-varying-network-jitter and packing-jitter and so on And by virtue of this algorithm, we can make low the dependency of network clock, which makes easy to synchronize and connect transparently at the ends point, we expect the proposed algorithm can be widely applied to the field of real -time multimedia communications.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.959-962
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• 2003

At the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.77-84
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• 2000

In this paper, we discuss a symbol clock extraction scheme based on maximizing the band-edge component of the transmitted signal frequency spectrum for applications to 51.84Mbps VDSL system which uses a 16-QAM. The major characteristics of the digital PLL are examined. In addition, we suggest an efficient design method of a sinusoidal look-up table which is used for NCO.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.12
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• pp.2263-2268
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• 2008

We investigated the malfunction and destruction characteristics of microcontroller devices under high power electromagnetic(HPEM) wave by magnetron. HPEM was rated at a microwave output of 0 to 1,000 W, at a frequency of 2,450${\pm}$50 MHz and was radiated from the open-ended standard rectangular waveguide(WR-340) to free space. The influence of different reset-, clock-, data-, and power supply-line lengths has been tested. The variation of the line length was done with flat cables. The susceptibility of the tested microcontroller devices was in general much influenced by clock-, reset-, and power supply-line length, little influenced by data-line length. Further the line length was increased, the malfunction threshold was decreased as expected, because more energy couples to the devices. The surfaces of the destroyed microcontroller devices were removed and the chip conditions were investigated with microscope. The microscopic analysis of the damaged devices showed component and bondwire destructions such as breakthroughs and melting due to thermal effects. The obtained results are expected to provide fundamental data for interpreting the combined mechanism of microcontroller devices in an intentional microwave environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1485-1490
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• 2005

Variable length code is an integral component of many international standards on image and video compression currently. Context-based Adaptive Variable Length Coding(CAVLC) is adopted by the emerging JVT(also called H.264, and AVC in MPEG-4). In this paper, we design an architecture for CAVLC encoder, including a coeff_token encoder, level encoder, total_zeros encoder and run_before encoder. The designed CAVLC encoder can encode one syntax element in one clock cycle. As a result of implementation by Vertex-1000e of Xilinx, its operation frequency is 68MHz. Therefore, it is very suitable for video applications that require high throughput.