Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Passband Digital Symbol Clock Recovery Scheme for 51.84Mbps VDSL QAM Receiver

51.84Mbps VDSL QAM 수신기를 위한 통과대역 디지털 심볼 클록 복원방식

  • Lee, Jae-Ho (Electronics and Telecommunications Research Institute) ;
  • Kim, Jae-Won (Dept.of Computer Engineering, Chonbuk National University) ;
  • Jeong, Hang-Geun (Dept.of Electronics Information Engineering, Chonbuk National University) ;
  • Jeong, Jin-Gyun (Dept.of Electronics Information Engineering, Chonbuk National University)
  • 이재호 (한국전자통신연구원) ;
  • 김재원 (전북대학교 컴퓨터공학과) ;
  • 정항근 (전북대학교 전자정보공학부) ;
  • 정진균 (전북대학교 전자정보공학부)
  • Published : 2000.03.01
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Abstract

In this paper, we discuss a symbol clock extraction scheme based on maximizing the band-edge component of the transmitted signal frequency spectrum for applications to 51.84Mbps VDSL system which uses a 16-QAM. The major characteristics of the digital PLL are examined. In addition, we suggest an efficient design method of a sinusoidal look-up table which is used for NCO.

본 논문에서는 51.84Mbps의 전송 속도를 갖고, 16-QAM 변조방식을 사용하는 VDSL(고속 디지털 가입자 루프) 시스템에서, 전송 신호 주파수 스펙트럼의 밴드-에지 성분을 최대화함으로써 심볼 클록(12.96㎒)을 복원하는 방식에 대해 논의한다〔1〕. 디지털 방식의 PLL에서 여러 가지 특성들이 조사되었으며, NCO(Numerically Controlled Oscillator)에서 사용하는 룩-업 테이블의 효율적인 설계 방식을 제시하였다.

Keywords

References

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