Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A NOR-type High-Speed Dual-Modulus Prescaler

NOR 형태의 고속 dual-modulus 프리스케일러

  • Seong, Gi-Hyeok (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology) ;
  • Kim, Lee-Seop (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology)
  • 성기혁 (한국과학기술원 전자전산학과) ;
  • 김이섭 (한국과학기술원 전자전산학과)
  • Published : 2000.03.01
Download PDF
⟨ Previous Next ⟩

Abstract

A dual-modulus prescaler divides the input signal by one of the moduli according to the control signal. In this paper, a new fast dual-modulus prescaler is proposed. The proposed prescaler has a ratioed-NOR structure different from a conventional ratioed-NAND structure. The proposed one can operate at a higher speed by using parallely connected NMOSs instead of using series-connected ones. HSPICE simulation results using HYUNDAI 0.65(m 2-poly 2-metal CMOS process parameters show that the maximum operating frequency of the proposed dual-modulus prescaler is 2.8㎓ with power consumption of 40.7㎽ at 5V supply voltage at $25^{\circ}C$. The proposed dual-modulus prescaler can be utilized for the frequency-synthesis in cellular radio front-ends.

dual-modulus 프리스케일러는 제어신호의 값에 따라 입력신호를 두 개의 모듈러스(modulus) 중에서 하나의 값으로 나누는 회로이다. 본 논문에서는 일반적인 ratioed-NAND구조가 아닌, ratioed-NOR구조를 가진 새로운 고속 dual-modulus 프리스케일러를 제안한다. 제안하는 회로는 NMOS를 직렬 연결하는 대신 병렬 연결함으로써 기존 회로보다 더 고속으로 작동한다. 현대 0.65(m 2-poly 2-metal CMOS 공정 파라미터를 사용한 HSPICE 모의 실험 결과, 25℃의 온도와 5V전원전압의 환경에서, 40.7㎽의 전력을 소모하고 최대 동작 주파수는 2.8㎓라는 것을 얻었다. 제안하는 dual-modulus 프리스케일러는 셀룰라 라디오의 입력단에서 주파수 합성을 하는 데에 이용될 수 있을 것이다.

Keywords

References

  1. H. singh, et al., 'GaAs prescalers and counters for Fast-settling frequency synthesizers,' IEEE J.Solid-State Circuits, vol. 25, no. 2, pp. 239-245, Feb. 1990 https://doi.org/10.1109/4.50310
  2. Y. Yamauchi, et al., 'A 15GHz monolithic two-modulus prescaler,' IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1632-1636, Nov. 1991 https://doi.org/10.1109/4.98983
  3. J. Yuan and C. Svensson, 'High-Speed CMOS Circuit Technique,' IEEE J. Solid- State Circuits, vol. 24, no. 2, pp. 62-70, Feb. 1989 https://doi.org/10.1109/4.16303
  4. B. Chang, J. Park, and W. Kim, 'A 1.2GHz CMOS Dual-Modulus Prescaler Using New Dynamic D~Type Flip-Flops,' IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 749-752, May 1996 https://doi.org/10.1109/4.509860
  5. Q. Huang and R. Rogenmoser, 'Speed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks,' IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 456-465, Mar. 1996 https://doi.org/10.1109/4.494209
  6. C. Yang, et aI., 'New Dynamic Flip-Flops for High-Speed Dual-Modulus Prescaler,' IEEE J. Solid-State Circuits, vol. 33, no. la, pp. 1568-1571, Oct. 1998 https://doi.org/10.1109/4.720406
  7. R. Racob Baker, et aI., CMOS circuit design, layout, and simulation. IEEE PRESS, pp. 242, 1998