• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.643-649
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• 2016

This paper presents a new image cache algorithm for real-time implementation of high-resolution color image warping. The cache memory is divided into four cache memory modules for simultaneous readout of four input image pixels in consideration of the color filter array (CFA) pattern of an image sensor and CFA image warping. In addition, a pipeline structure from the cache memory to an interpolator is shown to guarantee the generation of an output image pixel at each system clock cycle. The proposed image cache algorithm is applied to an FPGA-based real-time color image warping, and experimental results are presented to show the validity of the proposed method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.8
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• pp.80-85
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• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has 1.04[pF] resolution and can be used as a touch key.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.594-600
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• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.11
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• pp.1144-1149
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• 2009

This paper deals with the time synchronization problem over SpaceWire links. SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper, faster on-board data handling in spacecraft. The standard defines Time-Code for time distribution over SpaceWire network. When a Time-Code is transmitted, transmission delay and jitter is unavoidable. In this paper, a mechanism to remove Time-Code transmission delay and jitter over SpaceWire links is proposed and implemented with FPGA for validation. The proposed mechanism achieves high resolution clock synchronization over SpaceWire links, complies with the standard and can be easily adopted over SpaceWire network.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.982-985
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• 1999

An efficient technique to trade off speed for resolution is the sigma-delta modulation (SDM). This paper proposes a new SDM architecture to improve conversion rates and SNR(Signal-to Noise Ratio) by using master clock and four divided clock. The charateristics of the proposed SDM are simulated in MATLAB environment. and optimizing the capacitor sizes is done by iterative processing. other analog characteristics are simulated using 0.65${\mu}{\textrm}{m}$ n-well CMOS process, double poly and single metal. The result of simulation shows that more increasing the effective bits of internal ADC/DAC, bigger the improvement of SNR.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.1
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• pp.245-251
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• 2015

In this paper, we present a design of PWM-controlled driving device for backlights in LED systems. The system can control either the brightness of the entire screen of backlights of LCD driven by LED or illumination or contrast of each partial segment of the entire screen. The PWM-controlled driving device includes the shift register that shifts the series data according to the clock signal prior to the generation of parallel data. It is also is comprised of a number of registers, a number of counters, a number of comparators, and a number of synchronizing gates (producing the PWM-controlled signals). The proposed device for backlights in LED systems can generate the PWM-controlled signal with a high degree of resolution without the increase of clock frequency. It also contains the PWM-controlled circuit that disperses and restrains the quantized noise.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.7-14
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• 2012

A image quality is limited by a sample-and-hold circuit of the X-ray CMOS image sensor even though simple mos switch or bootstrapped clock circuit are used to get high quality sampled signal. Because distortion of sampled signal is produced by the charge injection from sample-and-hold circuit even using bootstrapped. This paper presents the 3D micro-inductor design methode in the CMOS process. Using this methode, it is possible to increase the ENOB (effective number of bit) through the use of micro-inductor which is calculated and designed in standard CMOS process in this paper. The ENOB is improved 0.7 bit from 17.64 bit to 18.34 bit without any circuit just by optimized inductor value resulting in verified simulation result. Because of this feature, micro-inductor methode suggested in this paper is able to adapt a mamography that is needed high resolution so that it help to decrease patients dose amount.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.166-171
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• 2004

This paper describes a CMOS time to digital converter (TDC) that measures the interval between two signals and converts to a digital signal. There are various methods to measure the time interval. But several architectures have a limitation in resolution and in conversion time. Moreover, they have complex algorithms. But the proposed TDC circuit has achieved a high resolution (25ps) by using a high-speed digital sampler and simple algorithm. The sampler detects when input signals comes into the TDC and output is coded. The proposed multiphase clock generator was also implemented to achieve 25p resolution.