• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2762-2764
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• 2001

In this study, we introduce and investigate a class of dynamic perceptron architectures, discuss a comprehensive design methodology and carry out a series of numeric experiments. The proposed dynamic perceptron architectures are called as Polynomial Neural Networks(PNN). PNN is a flexible neural architecture whose topology is developed through learning. In particular, the number of layers of the PNN is not fixed in advance but is generated on the fly. In this sense, PNN is a self-organizing network. PNN has two kinds of networks, Polynomial Neuron(FPN)-based and Fuzzy Polynomial Neuron(FPN)-based networks, according to a polynomial structure. The essence of the design procedure of PN-based Self-organizing Polynomial Neural Networks(SOPNN) dwells on the Group Method of Data Handling (GMDH) [1]. Each node of the SOPNN exhibits a high level of flexibility and realizes a polynomial type of mapping (linear, quadratic, and cubic) between input and output variables. FPN-based SOPNN dwells on the ideas of fuzzy rule-based computing and neural networks. Simulations involve a series of synthetic as well as experimental data used across various neurofuzzy systems. A detailed comparative analysis is included as well.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1137-1149
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• 2017

In order to reduce the cost, improve the efficiency and simplify the complicated control of existing isolated LED drivers, an improved boundary conduction mode (BCM) Buck ac-dc light emitting diode (LED) driver with extended output voltage and low total harmonic distortion is proposed. With a coupled inductor winding and a stacked output, its output voltage can be elevated to a much higher value when compared to that of the conventional Buck ac-dc converter, without sacrificing the input harmonics and power factor. Therefore, the proposed Buck LED driver can meet the IEC61000-3-2 (Class C) limitation and has a low THD. The operating principle of the topology and the design methodology of the ac-dc LED driver are presented. A 150 W ac-dc prototype was built in the laboratory and it shows that the input current harmonics meet the lighting standard. In addition, the THD is less than 16% at a typical ac input. The peak efficiency is higher than 96.5% at a full load and a normal input.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• Journal of Communications and Networks
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• v.3 no.4
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• pp.324-333
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• 2001

The Differentiated Services (Diffserv) framework has been proposed by the IETF as a simple service structure that can provide different Quality of Service (QoS) to different classes of packets in IP networks. IP packets are classified into one of a limited number of service classes, and are marked in the packet header for easy classification and differentiated treatments when transferred within a Diffserv domain. The Diffserv framework defines simple and efficient QoS differentiation mechanisms for the Internet. However, the original Diffserv concept does not provide a complete QoS management framework. Since traffic flows in IP networks are unidirectional from one network point to the other and routing paths and traffic demand get dynamically altered, it is important to monitor end-to-end traffic status, as well as traffic status in a single node. This paper suggests a distributed QoS monitoring method that collects the statistical data of each service class in every Diffserv router and calculates edge-to-edge QoS of the aggregated IP flows by combining routing topology and traffic status. A format modeling of edge-to-edge Diffserv flows and algorithms for aggregating edge-to-edge QoS is presented. Also an SNMP-based QoS management prototype system for Diffserv networks is presented, which validates our QoS management framework and demonstrates useful service management functionality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1B
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• pp.53-60
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• 2007

We investigate the end-to-end delay bounds in large scale networks with Differentiated services (DiffServ) architecture. It is generally understood that networks with DiffServ architectures, where packets are treated according to the class they belong, can guarantee the end-to-end delay for packets of the highest priority class, only in lightly utilized cases. We focus on tree networks, which are defined to be acyclic connected graphs. We obtain a closed formula for delay bounds for such networks. We show that, in tree networks, the delay bounds exist regardless of the level of network utilization. These bounds are quadratically proportional to the maximum hop counts in heavily utilized networks; and are linearly proportional to the maximum hop counts in lightly utilized networks. Considering that tree networks, especially the Ethernet networks are being accepted more and more for access networks as well as provider networks, we argue that based on these delay bounds DiffServ architecture is able to support real time applications even for a large network. Throughout the paper we use Latency-Rate (LR) server model, with which it has proven that FIFO and Strict Priority are LR servers to each flows in certain conditions.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1725-1734
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• 2016

This paper presents a novel seven-level (7L) voltage source converter for high-power medium-voltage applications. The proposed topology is an H-bridge connection of two nested neutral-point clamped (NNPC) converters and is referred to as an HNNPC converter. This converter exhibits advantageous features, such as operating over a wide range of output voltages, particularly for 10-15 kV applications, without the need to connect power semiconductors in series; high-quality output voltage; and fewer components relative to other classic seven-level topologies. A novel sinusoidal pulse width modulation technique is also developed for the proposed 7L-HNNPC converter to control flying capacitor voltages. One of the main features of the control strategy is the independent application of control to each arm of the converter to significantly reduce the complexity of the controller. The performance of the proposed converter is studied under different operating conditions via MATLAB/Simulink simulation, and its feasibility is evaluated experimentally on a scaled-down prototype converter.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.2
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• pp.114-122
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• 2004

This paper presents a novel single-stage active-clamp type high frequency resonant inverter. The proposed topology is integrated full-bridge boost rectifier as power factor corrector and active-clamp type high frequency resonant inverter into a single-stage. The input stage of the full-bridge boost rectifier works in discontinuous conduction mode(DCM) with constant duty cycle and variable switching frequency. So that a boost converter makes the line current follow naturally the sinusoidal line voltage waveform. By adding additional active-clamp circuit to conventional class-E high frequency resonant inverter, main switch of inverter part operates not only at Zero-Voltage-Switching mode but also reduces the switching voltage stress of main switch. Simulation results have demonstrated the feasibility of the proposed high frequency resonant inverter. Characteristics values based on characteristics estimation through circuit analysis is given as basis data in design procedure. Also, experimental results are presented to verify theoretical discussion. This proposed inverter will be able to be practically used as a power supply in the fields of induction heating applications, fluorescent lamp and DC-DC converter etc.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.18-29
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• 2002

Generally, the single-stage power factor corrected converter has a problem of high dc link voltage. In the case of high line voltage, especially, the dc link voltage is verb high under the light load condition. To solve this problem, a new single stage power factor corrected AC/DC converter has been proposed. The proposed converter has huck topology as a power factor corrector. To prove feasibility of the proposed converter, the design example of the proposed converter has been presented. The design considerations and experimental results for the proposed converter have been shown. The experimental results show that the line input current harmonics can meet IEC1000-3-2 Class D requirements for the range of line input voltage from 90Vrms to 260Vrms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9B
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• pp.1281-1286
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• 2010

Ant-based routing methods belong to a class of ant colony optimization algorithms which apply the behavior of ants in nature to routing mechanism. Since the topology of mobile ad-hoc network(MANET) changes dynamically, it is needed to establish paths based on the local information. Subsequently, it is known that routing in MANET is one of applications of ant colony optimization. In this paper, we propose a routing method, namely EPMAR, which enhances SIR in terms of route selection method and the process upon link failure. The performance of the proposed method is compared with those of AntHocNet and SIR. Based on he analysis, it is proved that the proposed method provided higher packet delivery ratio and less critical link failure than AntHocNet and SIR.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.167-172
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• 2006

In this paper, the 25W power amplifier for UHF band radio transceiver has been designed and realized. The power amplifier was composed of drive, power amplifier and control stages. Feedback topology and coaxial line baluns were used for wide band operation. The VDMOS, which has reliable performance for linearity and efficiency, was used for power device and designed to operate as push-pull amplification at Class AB Bias. The power amplifier designed in such a way was found to show stable AM modulation performance when voice signal was detected at the gate stage, with being designed and realized to meet output specifications of commercial air traffic control transmitter.