• Journal of Power Electronics
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• 제9권1호
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• pp.26-35
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• 2009

A high efficiency active clamp sepic-flyback converter is presented for fuel cell generation systems. The proposed converter is a superposition of a sepic converter mode and. flyback converter mode. The output voltages of the sepic converter mode and flyback converter mode can be regulated by the same PWM technique with constant frequency. By merging the sepic and flyback topologies, they can share the transformer, power MOSFET and active clamp circuit. The result has outstanding advantages over conventional active clamp DC-DC converters: high efficiency, high power density, and component utilization. Simulation results and experimental results are presented to verify the principles of operation for the proposed converter.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.403-405
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• 2008

This paper proposes an output inductor-less active clamp forward converter employing current boost-up circuit for high power density adaptor. By applying the proposed current boost-up circuit, the proposed converter has low conduction loss and low voltage ringing of the secondary rectifier. This paper presents the analysis of the proposed converter and a comparison between the proposed converter and the conventional converter through experiment.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.374-377
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• 2002

This paper presents dynamic analyses and control design of the current-mode controlled active-clamp forward-flyback converter. The circuit averaging technique is used to extract the small-signal circuit model for the power stage From the small-signal circuit model of the power stage, the open-loop transfer functions are derived and used for the compensation design. The analysis results are verified using an experimental converter that delivers a 3.3V/10A output from a $40\~60V$ input source.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2003년도 학술대회논문집
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• pp.311-314
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• 2003

In this paper, proposed circuit proposes that Active-Clamp-Circuits basis of a current-fed inverter linked type high frequency resonant dc-dc converter of conventional. and the paper the most of characteristics of the reduced high voltage stress main switches with active clamp circuits and output current constant with the resonant part consists of L, C resonant tank circuit. Also, the capacitor (C$_1$, C$_2$) connected in switches are a common using by resonance capacitor and ZVS capacitor. and circuit analysis used state equation of each part modes. Also we conform a rightfulness theoretical analysis by comparing a parameters values and simulation values obtained from simulation using Power MOS-FET as switching devices.

• 전기전자학회논문지
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• 제18권1호
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• pp.25-30
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• 2014

본 논문에서는 파워 클램프에 적용하기 위한 SCR 기반의 ESD 보호회로를 제안하였다. 기존 SCR 구조의 낮은 홀딩 전압에 의한 래치-업 문제를 개선하기 위해 n+ 플로팅 영역을 삽입하고 추가적인 n-웰과 p-웰까지 확장된 p+ 캐소드 영역을 통해 높은 홀딩 전압을 가질 수 있도록 고안되었다. 제안된 ESD 보호회로는 높은 홀딩 전압을 통해 정상 동작 상태에서의 래치-업 면역 특성을 확보하였으며, 우수한 ESD 보호 능력을 가진다. 제안된 ESD 보호회로는 Synopsys사의 TCAD 시뮬레이션을 통해 전기적 특성을 검증하였다. 시뮬레이션 결과, 트리거 전압은 약 27.3 V에서 최대 32.71 V 사이에서 변화하는 반면, 홀딩 전압은 4.61 V에서 최대 8.75 V까지 상승하는 것을 확인하였다. 따라서 제안된 ESD 보호회로는 트리거 전압은 기존 SCR과 비슷한 수준을 유지하면서 높은 홀딩 전압을 갖는다.

• ETRI Journal
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• 제37권1호
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of Power Electronics
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• 제15권1호
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• pp.86-95
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• 2015

An active clamp high step-up boost converter with a coupled inductor is proposed in this paper. In the proposed strategy, a coupled inductor is adopted to achieve a high voltage gain. The clamp circuit is included to achieve the zero-voltage-switching (ZVS) condition for both the main and clamp switches. A rectifier composed of a capacitor and a diode is added to reduce the voltage stress of the output rectifier diode. As a result, diodes with a low reverse-recovery time and forward voltage-drop can be utilized. Since the voltage stresses of the main and clamp switches are far below the output voltage, low-voltage-rated MOSFETs can be adopted to reduce conduction losses. Moreover, the reverse-recovery losses of the diodes are reduced due to the inherent leakage inductance of the coupled inductor. Therefore, high efficiency can be expected. Firstly, the derivation of the proposed converter is given and the operation analysis is described. Then, a steady-state performance analysis of the proposed converter is analyzed in detail. Finally, a 250 W prototype is built to verify the analysis. The measured maximum efficiency of the prototype is 95%.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.809-819
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• 2017

In this paper, a new coupled inductor DC-DC converter with a high step-up voltage gain is proposed. It is developed from a clamp-mode coupled-inductor boost converter by incorporating an additional capacitor and diode. The proposed converter is able to achieve the higher voltage gain, while still retaining the switch voltage clamp property of its predecessor. In the paper, operation and analysis of the proposed converter are described. Experimental results from a prototype converter are presented to verify the validity of the analysis. The prototype circuit attains the highest efficiency of 92.8%.

• 한국전기전자재료학회논문지
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• 제22권7호
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• pp.559-562
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• 2009

Due to the enormous progress achieved in light emitting diodes (LEDs) LEDs have been become a good solution for lightings. In LED driver for lighting applications, it is required high input voltage to drive more LEDs. Therefore, high-voltage should be changed to low-voltage to supply power for drive IC. In this paper, LED drive IC using voltage clamp bias circuit, it use a hysteretic-buck converter topology was proposed and verified through experiments.

• 전기학회논문지
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• 제59권6호
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• pp.1064-1069
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• 2010

Active clamp forward converter provides zero voltage switching, low voltage stress and wide input voltage range. The design technique leads to getting a higher efficiency under high switching frequency and optimal operating range. It is designed for notebook computer adapter with free input voltage and 19.5V/120W output ratings. The efficiency is measured to more than 90%. One of the most important circuit parts is the filter inductor besides the transformer in active clamp forward converter. In this paper, the process of inductor design is listed optimally.