• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.11
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• pp.952-957
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• 2003

We propose how to translate relay circuits to the EMFGs(Extended Mark Flow Graphs) formally and analyze the original one by using the mark flow of it. Firstly, the concepts of the output condition, the output-on condition and the output-off condition are introduced in the relay circuits. These can be used to find the structure and the operation of respective relay outputs but the sequential operations of them cannot be obtained from these. Secondly, a relay circuit is translated to the corresponding EMFG as the all output-on conditions and all output-off conditions of it are translated to EMFGs. For the adequate translation, the condition arc and the concepts of the generation transition and the degeneration transition are introduced, and the duality for the simplification of the result. Thirdly, we analyze the operation of the original circuit by analyzing the mark flow of the resulting EMFG. We can achieve easy and fast analysis based on the EMFG's operation algorithm. Finally, we apply these to the relay circuit for an electric furnace and analyze its operation with the mark flow of the resulting EMFG. The formal translation from relay circuits to EMFGs makes the analysis easy so that these results can be used to design, modelling, the fault detection and the maintenance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.17-22
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• 1974

In this paper, the problem of finding tests to detect faults in combinational logic circuits is considered. At first, the method of fault detection in fan-out-free irredundant circuits is derived, and the result is extended to the fan-out redundant circuits. A fan-out circuit is decomposed into a set of fan-out-free subcircuits by cutting the lines at the internal fan-out points, and the minimal detecting test. sets for each subcircuit are found separately. And then, the compatible tests from each test set are combined maximally into composite tests to generate primary input binary vectors. By this procedure. the minimal complete test sets for reconvergent fan-out circuits are easily found and the detectable and undetectable faults are also classified clearly.

• Journal of electromagnetic engineering and science
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• v.13 no.1
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• pp.54-61
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• 2013

An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.266-269
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.105-114
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• 2000

Delay testing is essential for assurance of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new test method and algorithm are devised which can be used for both stuck-at testing and delay testing. To apply the new test method, a new scan flip-flop is implemented. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased drastically over conventional scan techniques.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.4
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• pp.12-17
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• 1976

This paper deals with characteristics and analysis of the Universal Logic Modules as well as TULM, QULM and SULM. Studies are made on minimization in Storms of symmetric circuits and theoretical stuides are made by using the symmetric functions The symmetric circuits of the ULM are realized by employing 54/74 ICs, An oscillator circuit of 10KHz. is constructed based on the ULM. The experimental results gave a good agreement with the theoretical Minimization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1661-1668
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• 2016

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

• Journal of Communications and Networks
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• v.9 no.1
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• pp.93-104
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• 2007

Traffic grooming, in which low-rate circuits are multiplexed onto wavelengths, with the goal of minimizing the number of add-drop multiplexers (ADMs) and wavelengths has received much research attention from the optical networking community in recent years. While previous work has considered various traffic models and network architectures, protection requirements of the circuits have not been considered. In this paper, we consider survivable traffic grooming, or grooming traffic which contains a mix of circuits that need protection and that do not need protection. We assume a unidirectional ring network with all-to-all symmetric traffic with $t\geq1$ circuits between each node pair, of which s require protection. As it turns out, survivable traffic grooming presents a significant tradeoff between the number of wavelengths and the number of ADMs, which is almost non-existent in non-survivable traffic grooming for this type of traffic. We explore this tradeoff for some specific cases in this paper. We also present some new results and solution methods for solving certain non-survivable traffic grooming problems.