Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Efficient Delay Test Algorithm for Sequential Circuits with a New Scan Design

순차 회로의 효율적인 지연 고장 검출을 위한 새로운 테스트 알고리듬 및 스캔 구조

  • 허경회 (延世大學校 電氣工學科) ;
  • 강용석 (延世大學校 電氣工學科) ;
  • 강성호 (延世大學校 電氣工學科)
  • Published : 2000.11.01
Download PDF
⟨ Previous Next ⟩

Abstract

Delay testing is essential for assurance of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new test method and algorithm are devised which can be used for both stuck-at testing and delay testing. To apply the new test method, a new scan flip-flop is implemented. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased drastically over conventional scan techniques.

지연 고장을 위한 테스트는 디지털 회로의 속도와 직접도가 크게 향상되면서 필수적인 것으로 생각되고 있다. 그러나, 순차 회로에는 상태 레지스터들이 있기 때문에, 지연 고장을 검출하는 것이 쉽지 않다. 이러한 난점을 해결하기 위해 회로의 단일 고착 고장과 지연 고장을 효율적으로 검출할 수 있는 새로운 테스트 방법과 알고리듬을 개발하였고 이를 적용하기 위한 새로운 구조의 스캔 플립-플롭을 제안한다. ISCAS 89 벤치마크 회로에 대한 실험을 통해 지연 고장 검출률이 기존의 전통적인 스캔 테스트 방법에 비해 현격하게 향상된 것을 알 수 있다.

Keywords

References

  1. V. Iyengar, B. Rosen, and I. Spillinger, Delay Test Generation Algebra and Algorithms, Proc. of International Test Conference, pp. 867-876, 1988 https://doi.org/10.1109/TEST.1988.207874
  2. J. Waicukauski, E. Lindbloom, B. Rosen and V. Iyengar, Transition Fault Simulation, IEEE Design and Test, pp. 32-38, April 1987
  3. Hsieh, E. P., Rasmussen, R. A., Vidunas, L. J., Davis, W. T., Delay Test Generation, Proc. of Design Automation Conference, pp. 486-491, June 1977
  4. Smith, G. L. Model for Delay Faults Based upon Paths, Proc. of International Test Conference, pp. 342-349, November 1985
  5. A. Saldanha, R. K. Brayton and A. L. Sangiovanni-Vincentelli, Equivalence of Robust Delay-fault and Single Stuck-fault Test Generation, Proc. of Design Automation Conference, pp. 173-176, 1992 https://doi.org/10.1109/DAC.1992.227841
  6. K. T. Cheng and H. C. Chen, Delay Testing for Non-robust Untestable Circuits, Proc. of International Test Conference, pp. 954-961, 1993 https://doi.org/10.1109/TEST.1993.470604
  7. W. Ke and P. R. Menon, Synthesis of Delay verifiable Combinational Circuits, IEEE Trans. on Comput., vol. 44, pp. 213-222, February 1995 https://doi.org/10.1109/12.364533
  8. Bill Underwood, Wai-On Law, Sungho Kang, Haluk Konuk, Fastpath: A Path-Delay Test Generator for Standard Scan Designs, Proc. of International Test Conference, pp. 154-163, 1994 https://doi.org/10.1109/TEST.1994.527946
  9. M. Schulz et al., Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults, Proc. of Fault Tolerant Computing Symp., 1989 https://doi.org/10.1109/FTCS.1989.105541
  10. J. D. Lesser and J. J. Schedletsky, An Experimental Delay Test Generator for LSI logic, IEEE Trans. on Comput., pp. 235-248, March 1980
  11. Sungho Kang, Wai-On Law, and Bill Underwood, Path-Delay Fault Simulation for a Standard Scan Design Methodology, Proc. of International Conference on Computer Design, 1994 https://doi.org/10.1109/ICCD.1994.331926
  12. J. Savir, Scan Latch Design for Delay Test, Proc. of International Test Conference, pp. 446-453, 1997 https://doi.org/10.1109/TEST.1997.639650