• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.105-111
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• 2007

In this paper, we designed and fabricated a 3-dB tandem coupler using air-bridge technology for millimeter-wane monolithic integrated circuits, operating at W-band($75{\sim}110\;GHz$) frequency. Tightly edge-coupled CPW line has low directivity due to different even-mode and odd-mode phase velocity. To overcome this disadvantage, a 3-dB tandem coupler which comprises the two-sectional weakly parallel-coupled lines with equal phase velocity was designed at W-band. The proposed coupler was fabricated using air-bridge technology to monolithically materialize the uniplanar coupler structure instead of conventional multilayer or wire bonded structure. From the measurements, the coupling coefficient of $2.9{\sim}3.6\;dB$ and the good phase difference of $91.2{\pm}2.9^{\circ}$ were obtained in broad frequency range of $75{\sim}100\;GHz$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.477-480
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• 2002

Si-O-C(-H) thin film with a tow dielectric constant were deposited on a P-type Si(100) substrate by an inductively coupled plasma chemical vapor deposition (ICPCVD). Bis-trimethylsilymethane (BTMSM, H$_{9}$C$_3$-Si-CH$_2$-Si-C$_3$H$_{9}$) and oxygen gas were used as Precursor. Hybrid type Si-O-C(-H) thin films with organic material have been generated many voids after annealing. Consequently, the Si-O-C(-H) films can be made a low dielectric material by the effect of void. The surface characterization of Si-O-C(-H) thin films were performed by SEM(scanning electron microscope). The characteristic analysis of Si-O-C(-H) thin films were performed by X-ray photoelectron spectroscopy (XPS).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.517-531
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• 1999

This paper presents the development of the 2-mode variable gain high power amplifier for a transmitter of INMARSAT-M operating at L-band(1626.5-1646.5 MHz). This SSPA(Solid State Power Amplifier) is amplified 42 dBm in high power mode and 36 dBm in low power mode for INMARSAT-M. The allowable error sets +1 dBm of an upper limit and -2 dBm of a lower limit, respectively. To simplify the fabrication process, the whole system is designed by two parts composed of a driving amplifier and a high power amplifier, The HP's MGA-64135 and Motorola's MRF-6401 are used for driving amplifier, and the ERICSSON's PTE-10114 and PTF-10021 are used the high power amplifier. The SSPA was fabricated by the circuits of RF, temperature compensation and 2-mode gain control circuit in aluminum housing. The gain control method was proposed by controlling the voltage for the 2-mode. In addition, It has been experimentally verified that the gain is controlled for single tone signal as well as two tone signals. The realized SSPA has 42 dB and 36 dB for small signal gain within 20 MHz bandwidth, and the VSWR of input and output port is less than 1.5:1 The minimum value of the 1 dB compression point gets 5 dBm for 2-mode variable gain high power amplifier. A typical two tone intermodulation point has 32.5 dBc maximum which is single carrier backed off 3 dB from 1 dB compression point. The maximum output power of 43 dBm was achieved at the 1636.5 MHz. These results reveal a high power of 20 Watt, which was the design target.the design target.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.634-639
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• 2006

In this paper an MMIC 2-stage power amplifier is designed and fabricated for 5GHz wireless LAN applications using $0.5{\mu}m$ gate length PHEMT transistors. The PHEMT gate width is optimized in order to meet the linearity and efficiency of the MMIC power amplifier. The $0.5{\mu}m\times600{\mu}m$ PHEMT for the drive stage and $0.5{\mu}m\times3000{\mu}m$ PHEMT for the amplification stage are the optimized sizes to achieve more than 25dBc of third order IMD at the power level of 3dB back-off from the input P1dB and more than 22dBm output power under a supply voltage of 3.3V. The two-stage MMIC power amplifier is designed to be used for the both of HIPERLAN/2 and IEEE 802.11a because of its broadband characteristics. The fabricated PHEMT MMIC power amplifier exhibits a 20.1dB linear power gain, a maximum 22dBm output power, a 24% power added efficiency under 3.3V supply voltage. The input and output on-chip matching circuits are included on a chip of $1400\times1200{\mu}m^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.3
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• pp.298-306
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• 2014

The railway signalling system for safe train operation regulates the train speed to ensure the safety distance between consecutive trains by using wayside facilities such as track circuits and interlocking systems. In addition, this signalling system controls the trackside equipment such as a railway point along the train line. This ground-equipment-based train control systems require high CAPEX and OPEX. To deal with these problems, the train control system using the on-board controller has been recently proposed and its related technologies have been widely studied. The on-board-controller-based train control system is that the on-board controller can directly control the trackside equipment on the train line. In addition, if this system is used, the wayside facilities can be simplified, and as a result, the efficient and cost-effective train control system can be realized. To this end, we have developed the prototypes of the on-board controller and wayside object control units which control the point and crossing gate and performed the integrated operation simulation in a testbed. In this paper, before the field test of the on-board-controller-based train control system, we perform the preliminary field trial including the installation test, wireless access test, interface test with other on-board devices, and normal operation test.

• Journal of the Korean Chemical Society
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• v.48 no.6
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• pp.553-560
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• 2004

In this experiment, a three dimensional structure analysis was carried out to examine the surface defects of semiconductor made artificially on known scale. It was investigated the three dimensional imaging according to the sample depth and the thermal diffusivity as well as the carrier transport properties. The thermal diffusivity measurement of the intrinsic GaAs semiconductor was also analyzed by the difference of frequency-dependence photoacoustic signals from the sample surface of different conditions. Thermal properties such as thermal diffusion length or thermal diffusivity of the Si wafer with and without defects on the surface were obtained by interpreting the frequency dependence of the PA signals. As a result, the photoacoustic signal is found to have the dependency on the shape and depth of the defects so that their structure of the defects can be analyzed. This method demonstrates the possibility of the application to the detection of the defects, cracks, and shortage of circuits on surface or sub-surface of the semiconductors and ceramic materials as a nondestructive testing(NDT) and a nondestructive evaluation(NDE) technique.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.