• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.650-656
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• 2016

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.

• Journal of Industrial Technology
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• v.13
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• pp.59-69
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• 1993

Using two current conveyors with the grounded capacitors and resistors, this paper proposed equivalent circuits which can realize the floating L and the floating FDNR. To find out their characteristics, we experiment with these circuits instead of the floating L of the low-pass filter and the floating FDNR of the high-pass filter respectively. Comparing theoretical values with experimental ones, values of the proposed floating L represent the error of 5 percents in the frequency range from 5 KHz to 25 KHz, and values of the floating FDNR represent the error of 5 percents in the range from 8 KHz to 25 KHz. So the proposed floating L and the FDNR circuits are expected to be implemented with current conveyors of an IC.

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.162-171
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• 2009

Linear regulator for generating various voltages in satellite electronics is implemented with radiation harden regulator chips or simple linear regulator circuits. For implementing linear regulator circuits, the detail design can be various. But the worst case analysis method and interesting analysis items for the linear regulator circuits can be generalized. So this paper describes and summarizes the general worst case analysis method and interesting analysis items for the conventional linear regulator circuits.

• Publications of The Korean Astronomical Society
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• v.13 no.1 s.14
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• pp.123-128
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• 1998

The Blandford-Znajek process, which extracts the rotational energy of the supermassive black hole at the center of an active galactic nucleus, is now well explained and educated through the electronic circuit analysis established by Macdonald and Thorne. The Macdonald-Thorne circuits consist of the batteries and resistances of the central black hole and the astrophysical region around the accretion disk. In this letter we will consider the possibility whether we can connect coils and condensers in such circuits or not. If possible, that may explain a sudden corona-phenomenon in an active galactic nucleus. We conclude that a flash of order $\~5\times10^{40}\;ergs\;s^{-1}$ can occur around a $\~10^9M_\bigodot$ black hole through this process.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.642-645
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• 2003

We proposed new current source and mirror circuits insensitive to $V_{th}$ variation of poly-Si TFTs. The proposed circuits have been verified by SPICE simulation using poly-Si TFT model. The error currents of the proposed current source and current mirror circuits caused by $V_{th}$ variation reduced less than 6.6% and 4.5% of that of conventional ones, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.11-22
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• 1997

This paper presents the design and implementation of an efficient algorithm for detecting untestable paths in multi-level circuits. Transforming multi-level circuit into a multiplexor-based one through BDD(binary decision diagram)construction, the proposed algorithm detects untestable paths in the transformed circuits. By constructing ENF (equivalent normal form) only for reconvergent paths, the proposed system detects and removes untestable paths efficiently in terms of the run-time and memory usage. Experimental results for MCNC/ISCAS benchmark circuits show that the system efficiently detects and removes untestable paths. The run-time and memory usage have been reduced by 37.7% and 60/9%, respectively, comapred to the previous methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.78-84
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• 1984

We propose a new algorithm which detects stuck-open faults in CMOS circuits without being affected by time skews not using additional circuits. That is, the Domino CMOS circuit structure is used as circuit configurations and the clocking gate in this circuit is modeled as one branch, then test sequence is generated by using the transition test. Also, it is verified by applying this algorithm implemented in VAX II/780 to arbitrary CMOS circuits that all of stuck-open faults which were not detected because of time skews in conventional methods is detected.

• Journal of electromagnetic engineering and science
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• v.13 no.3
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• pp.141-150
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• 2013

Multiplexers based on isolation circuits made of metamaterial lines are proposed and studied. The new approach provides unique advantageous features beneficial to system designer. For instance, there is no need to modify the filters used in multiplexers. Also, the design process is straightforward. In this paper, two types of multiplexers based on metamaterial isolation circuits are presented, and their operation concepts are explained. Also, theories and design process of isolation circuits are presented to help readers design and fabricate proposed multiplexers. For verifying the concepts, two types of triplexers and two types of quadruplexers are designed and fabricated. All filters used in the multiplexers are commercial surface acoustic wave filters. The measured results are well matched with the simulation results.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.3
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• pp.27-34
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• 2012

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.