• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.2000-2003
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• 2002

In this paper, an IC chip of a cell- network type circuit constructed with 1-dimensional chaos circuits is reported. The circuit, is designed by sing switched-current (Sl) techniques. In the proposed circuit, by controlling connections of cells, an S- dimensional circuit (S ＝ 1, 2, 3,…) and a synchronization system can be constructed easily. Furthermore, in spite of faults of a few cells, the circuit can reconstruct above-mentioned systems only to change connections of cells. This feature will open up new vista for engineering applications which are used in a distance place such as space, deep sea, etc. since it is difficult to repair faults of these application systems. To investigate the characteristics of the circuit, SPICE simulations are performed. The VLSI chip is fabricated from the layout design using a CAD tool, MAGIC. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• The Journal of the Acoustical Society of Korea
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• 제20권1E호
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• 반도체디스플레이기술학회지
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• 제4권4호
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• pp.27-31
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• 2005

This article contains the development of FPC bonder that used for repair or trial product. Nowadays, in FPO module process (including PDP) accept the thermo-compress bonding method when attach FPC(Flexible Printed Circuit Board), TCP(Tape Carrier Package) and COF(Chip on the FPC) by ACF(Anisotropic Conductive Film). This system consists of ACF attachment part, pre-bonding part, main bonding part, loading / unloading part. This composition is a stand-alone system, not an in-line system. Hereafter, this composition should be developing into in-line system in all area of FPD industry.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• 한국산업융합학회 논문집
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• 제25권3호
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• pp.333-340
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• 2022

Recently, the use of large-capacity secondary batteries for electric vehicles is rapidly increasing, and accordingly, the demand for technologies and equipment for battery reliability evaluation is increasing significantly. The existing short circuit test equipment for evaluating the stability of the existing secondary battery consists of relays, MCs, and switches, so when a large current is energized during a short circuit, contact fusion failures occur frequently, resulting in high equipment maintenance and repair costs. There was a disadvantage that repeated testing was impossible. In this paper, we developed an electronic short circuit test device that realizes stable switching operation when a large-capacity power semiconductor switch is energized with a large current, and applied smart ICT technology to this electronic short circuit stability test system to achieve high speed and high precision through communication with the master. It is expected that the inspection history management system based on data measurement, database format and user interface will be utilized as essential inspection process equipment.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 추계학술대회 논문집
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• pp.279-280
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.295-296
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• 2006

We developed wire frame drive unit based on SMA for the 3D Shape display. Our basic concept is wire frame combination connected with a chain form which can create various shapes and it compared with pin array mechanism which is not able to display mushroom shape. It imitates antagonist mechanism of human musculoskeletal system. we create similar motion using repair-relaxation mechanism and locking mechanism by SMA. Therefore, in this paper, we propose SMA control solution for actuating repair-relaxation mechanism and locking mechanism. In our control system. we use optical sensor and quantitative angle between wire frames for closed loop control. And we supply amplified current for SMA by circuit composed of transistor and apply PWM signal to circuit for efficient control. So, wire frame drive unit enable diversity angle control based on sensor data. And then combination of wire frame drive units will create various objects.

• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.586-592
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• 2018

본 논문은 140W 급 저면적 LED 전원 제어 회로 설계를 위해 다양한 기능이 집적된 HIC를 제안한다. 제안된 HIC는 정전압/정전류 구동회로, 단락 보호회로, 내부 정전압회로, dimmer 회로를 하나로 집적해, 제작 시 기존 시스템 대비 PCB 가로 길이를 16% 절감하는 효과를 보였다. 다양한 실험을 통해 HIC 내부에 설계된 각 블록의 성능을 검증했고, (정전압 구동회로 변동률 2.9%, dimmer 회로 오차 5%이내, 720 mA에서 안정적인 short protection) 제안된 HIC를 적용해 시스템에서 필요로 하는 전력 대비 PCB 면적을 상당히 줄일 수 있기 때문에, 제작 시간의 대부분을 차지하는 PCB 제조시간을 단출할 수 있는 효과와 전원 제어 회로에서 발생하는 불량에 대해 기존과 같이 PCB 전체를 교체하지 않고 HIC만 교체할 수 있도록 하여 유지/보수를 쉽게 할 수 있는 효과를 기대한다.

• 정보학연구
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• 제3권3호
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• pp.57-65
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• 2000

본 논문에서는 내장된 SDRAM 에 대한 기능 및 AC 변수를 테스트하는 BIST 회로의 알고리듬 및 회로 구현을 기술하였다 제안된 BIST 회로를 사용하여 내장된 SDRAM 의 고장난 비트 셀의 어드레스 위치를 출력시킴으로써 Redundancy 회로 사용에 관한 정좌를 제공하도록 설계하였다. 또 실지 동작 주파수에서의 내장된 SDRAM 의 AC 변수에 대한 테스트를 수행하여 메모리의 오동작이 발생된 경우 어떤 AC 변수가 설계 사양을 벗어나는지를 출력하도록 구현하였다. $0.25\mu\textrm{m}$ 셀 라이브러리를 이용하여 회로 합성하는 경우 전체 게이트 수는 약 4,500 개 정도이고, Verilog 레지스터 전송 언어를 사용하여 설계 및 시뮬레이션을 통하여 검증하였다. 하나의 AC 변수에 대해서 2Y-March 14N 알고리듬으로 테스트하는 경우 100Mhz 동작 주파수에서 테스트 시간은 200ms 정도이다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.501-503
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• 2005

The improvement of load following operation of the thermal power plant is influenced to the electrical quality. Analysis of boiler, turbine, and governor system, and the study of control algorithm are preceded. The thermal power plant is operated by various control systems. In the case of faulty governor system, it takes long days to solve the problem and impossible to repair the mechanism without outage. A non-planned out-age is taken into consideration because of economical power production. In this paper, to clear the continuous swings of an old turbine governor system(YEOSU #1), the trend, the control logic, and the hydraulic mechanism are analyzed, and then the control circuit with ADAPT function and the 1st order lag circuit are inserted and modified. After that, the power plant comes to automatic governor control operation.