• 한국정밀공학회지
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• 제21권12호
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• pp.44-51
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• 2004

In a micro-EDM, it is well known that an RC circuit is suitable as a discharge circuit because of its low pulse width and relatively high peak current. To increase machining speed without changing unit discharge energy, charge resistance should be decreased. But, when the resistance is very low, continuous (or normal) arc discharge occurs, electrode wear increases and machining speed is reduced remarkably. In this paper, an RC circuit with transistors is used in a micro-EDM. Experimental results show that the RC circuit with transistors can cut off a continuous (o. normal) arc discharge effectively if the duty factor and switching period of the transistor are set up optimally. Through experiments with varying charge resistances, it is shown that the RC circuit with transistors has about two times faster machining speed than that of an RC circuit.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.548-551
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• 2004

Magnetostrictive actuators have seen increasing use in fine positioning system because it has many advantages such as friction free, resolution of ${\mu}{\textrm}{m}$ or nm scale, and powerful output force. Usually, the magnetic circuit of magnetostrictive actuator has components which are flux return path, coil, and magnetostrictive material. It is classified in two types according to existence of the permanent magnet. The magnetic circuit having optimal performances transfer magnetic field which is obtained by providing input current at coil without energy loss. This paper described mathematical model of magnetic circuit for getting design variables. The modeling equation is obtained from the relations between flux and reluctance of the magnetic equivalent circuit. Also, finite element analysis has been used to study the performance of magnetic circuit according to change of design variables such as existence and shape of the permanent magnet, flux return path etc. The modification of dimensions enables us to optimize magnetic circuit.

• Journal of Electrical Engineering and Technology
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• 제7권5호
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• pp.778-783
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• 2012

The synthetic short-circuit making test to adequately stress the circuit breaker has been specified as the mandatory test duty in the IEC 62271-100. The purpose of this test is to give the maximum pre-arcing energy during making operation. And this requires the making operation with symmetrical short-circuit current that is established when the breakdown between contact gap occurs near the crest of the applied voltage. Also, if the interrupting chamber of circuit breakers is designed as the type of common enclosure or the operation is made by the gang operated mechanism that three-phase contacts are operated by one common mechanism, three-phase synthetic making test is basically required. Therefore, several testing laboratories have developed and proposed their own test circuits to properly evaluate the breaker performance. With these technical backgrounds, we have developed the new alternative three-phase making circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.179-182
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• 2003

A simulation on bootstrapping circuit has been performed by modelling a coaxial cable as a transmission line. It is shown that the bootstrapping circuit could be unstable due to the transmission line effect though an ideal amplifier is used. While the conventional bootstrapping circuit does not cancel the input capacitance of the input buffer, a new bootstrapping circuit that cancels input capacitance of the input buffer has been proposed. The proposed bootstrapping circuit consists of the input buffer of which gam is larger than 1 and a feedback resistor to control the loop gain. The proposed bootstrapping circuit has higher input impedance than that of the conventional circuit.

• 전력전자학회논문지
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• 제17권4호
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• pp.368-376
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• 2012

According to developed distributed generators, Solid State Circuit Breaker(SSCB) is essential for high power quality of DC Grid. In this paper, a simple and new structure of DC SSCB with a fast circuit breaker and fault current limiter is proposed. It can help to choice low specification of elements because of the limiting of fault current and achieve economic efficiency for minimizing auxiliary SCRs. Also all of SCRs have little switching loss because they operate under ZVS and ZCS. Through simulations and experiments of short-circuit fault, the performance characteristic of proposed circuit is verified and a guideline is so suggested that the DC SSCB is applied for a different DC grid using formulas.

• 한국전기전자재료학회논문지
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• 제27권11호
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1597-1609
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• 2015

This paper introduces the fundamentals of the conventional LC low-pass filter circuit in the fractional domain. First, we study the new fundamentals of fractional-order LC low-pass filter circuit including the pure real angular frequency, the pure imaginary angular frequency and the short circuit angular frequency. Moreover, sensitivity analysis of the impedance characteristics and phase characteristics of the LC low-pass filter circuit with respect to the system variables is studied in detail, which shows the greater flexibility of the fractional-order filter circuit in designs. Furthermore, from the filtering property perspective, we systematically investigate the effects of the system variables (LC, frequency f and fractional orders) on the amplitude-frequency characteristics and phase-frequency characteristics. In addition, the detailed analyses of the cut-off frequency and filter factor are presented. Numerical experimental results are presented to verify the theoretical results introduced in this paper.

• Journal of information and communication convergence engineering
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• 제6권3호
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• 대한전기학회논문지
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• 제43권2호
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• pp.244-250
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• 1994

This paper presents the design of a new turn-off gate drive circuit for GTO which can accomplish faster turn-off switching. The major disadvantage of the conventional turn-off gate drive technique is that it has a difficulty in realizing high negative diS1GQT/dt because of VS1RGM(maximum reverse gate voltage) and stray inductances of turn-off gate drive circuit[1~2]. The new trun-off gate drive technique can overcome this problem by adding another turn-off gate drive circuit to the conventional turn-off gate drive circuit. Simulation and experimental results of the new turn-off gate drive circuit in conjunction with chopper circuit verify a faster turn-off switching performance.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1192-1195
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• 2005

This paper presents the realization of a multiple-input maximum circuit, which is operated in a current-mode. The proposed circuit operates with bi-directional input current signal and employs 5n+4 transistors for n inputs. The realization method is suitable for fabrication using CMOS technology. The proposed circuit is useful building block for the real-time systems. The performances of the proposed bi-directional maximum circuit were studied using the PSPICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values.