Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
권호 표지

Design of a Frequency Locked Loop Circuit

  • Choi, Jin-Ho (Dept. of Computer Engineering, Pusan University of Foreign Studies)
  • Published : 2008.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

Keywords

References

  1. R. E. Best, Phase-Locked Loops: Theory, Design and Applications, New York:McGraw-Hill, 1984
  2. A. Djemouai, M. Sawan and M. Slamani, 'New Circuit Techniques Based on a High Performance Frequency-to-Voltage Conversion,' Proceedings of IEEE Int. Conf. Electronics Circuits and Systems, pp. 13-16, 1999
  3. Jin-Ho Choi and Young-Jung Yu, 'Temperature Stable Frequency-to-Voltage,' The Journals of The Korea Institute of Maritime Information & Communication, vol. 11, no. 5, pp. 949-954, May 2007
  4. M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, Prentice Hall, 1997, pp. 173-193