• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1418-1421
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• 2003

The Vacuum circuit breaker is a kind of power circuit breaker and protect electric devices from over-current. In this paper we built a dynamic model of VCB driving mechanism using ADAMS. The development of the new circuit breaker with less energy and more compactable mechanism is focused. Through the dynamic model, the concept design of the new circuit breaker with less energy and more compactable mechanism is proposed, and then the detailed design is carried out through the design process based on the dynamic model.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10b
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• pp.569-572
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• 1992

This paper describes a new method of pseudorandom testing of a digital circuit by use of correlation method and a neural network. The authors have recently proposed a new method of fault diagnosis of logical circuit by applying a pseudorandom M-sequence to the circuit under test, calculating the crosscorrelation function between the input and the output, and comparing the crosscorrelation functions with the references. This method, called MSEC method, is further extended by using a neural network in order to not only detect the existence of faults but also find the place or location of the faults. An experiment by using a simple digital circuit shows enough applicability of this method to industrial testing of circuit board.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.4
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• pp.7-16
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• 1971

A negative resistance element in the form of current control can be obtained by using a pair transistor circuit. This negative resistance element can be used in the generation of square pulse, and also in the realization of pulse width modulation circuit by superposing signal current on its bias current. The each bias current of pair circuit increases alternatively according to the polarity of the input signal. In order to satisfy this condition, a modified full wave rectification circuit has been adopted for supplying the input signal. Theoritical analysis of pulse times and design guidances for practical modulation circuit parameters are presented.

• Proceedings of the KSR Conference
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• 2000.11a
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• pp.602-609
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• 2000

This study is concerned with analysis and reliability evaluation of LV circuit in Cab Cubicle system which controls train to keep safety in High Speed Train. LV circuit is operated with diagnosis system as safety system. In this paper, we suggest a design and an implementation method to analyze LV circuit or trace fault area in LV circuit. This simulator uses 28 package modules and examines input and output by equations. So, user can trace where is fault area. The implemented system can be expected to be useful for long term test and evaluation of circuit in high speed train systems. We expect reduction to diagnosis area or repair time by this simulator.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.107-115
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• 2012

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.231-234
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• 2002

In this paper, we propose an efficient bias circuit for hearing aid using discrete BJT. The collector feedback bias circuit, widely used for the hearing aid, has a resister for negative feedback. As the resistor affects AC and DC simultaneously, it is quite difficult to adjust amplifier gain without changing DC bias point. The previous bias circuit also has weak point to be oscillated by the positive feedback of power noise if gain of hearing aid is high. In the proposed circuit, we can reduce the two weak points of the previous circuit by adding a resistor which is ${\beta}$ times larger than collector resistor between base of BJT and power supply.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.8-12
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• 2002

Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.17-20
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• 2002

A complex single flux quantum(SFQ) circuit could be made up of various elementary cells such as JTL(Josephson transmission line), Splitter, XOR, DC/SFQ, SFQ/DC, T flip-flop, ‥‥, etc. In this work, we have designed and simulated a SFQ circuit, which consists of DC/SFQ, JTL and SFQ/DC, based on Nb/AlO$_{x}$Nb Josephson junction technology From the simulation, we could obtain the margins for various circuit parameters. And also we have successfully operated the circuit, which was fabricated with the same design, up to the input signal frequency of about 20 GHz.z.