• Journal of the Korean Society for Precision Engineering
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• v.17 no.7
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• pp.45-51
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• 2000

지난 세기부터 MEMS 제작 기술을 이용하여 만들어진 시스템들을 의학이나 생물학적인 용도로 응용하기 위한 많은 연구가 활발히 이루어져 왔다. 기술적인 측면에서 이러한 연구들은 MEMS 분야의 초창기에 강조되어 온 표면 및 몸체 미세 가공 기술(surface ＆ bulk micromachining)과 같은 미세 구조물 제작 기술의 발전에 힘입은 바 크다. 그러나 MEMS 기술이 점차 발전되어 오면서, 가공 기술이 고도화되고 미세 시스템의 구조가 점차 복잡해짐에 따라, 많은 연구들이 단순한 가공기술을 넘어 미세 시스템을 조립하고 집적화할 수 있는 기술, 접합 (bonding) 기술, 패키징 (packaging) 기술, 3차원 형상의 제작 기술, 실리콘(silicon)이나 유리(glass)가 아닌 다른 재료를 이용한 미세 가공 기술 등의 개발을 중심으로 이루어지고 있다.(중략)

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.146-149
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• 2007

1) 자체 제작한 NCP인 A, B, C 3종은 상용화 제품에 비해 도포성에 관련한 특성은 우수한 것으로 나타났으나 Tg 등의 열특성은 개선이 필요한 것으로 판단된다. 2) 접합강도의 경우 4종의 큰 차이가 없었으나 필러가 비교적 적은 조성인 B 조성의 경우 가장 큰 접합강도를 나타냈다. 3) NCP A, B, C 3종에 대한 접속저항 측정 결과 필러가 가장 많은 C의 경우가 가장 높은 저항 값을 보였으며 이는 가속 고온 고습 시험에 대한 결과에서도 급격한 접속률 감소를 통해 확인할 수 있다. 4) 시간에 따른 접속저항의 급격한 증가는 NCP 성분 중 친수성을 가진 물질이 있는 것이 원인이라 판단되며 이에 대한 개선을 통해 고습에 대한 신뢰성을 향상시킬 수 있을 것으로 보인다.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09b
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• pp.1207-1208
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• 2006

We developed the copper core ball electroplated with Sn-Ag-Cu of the eutectic composition which used mostly as Pb free solder ball with high reliability. In order to search for the practicality of this developed copper core ball, the evaluation was executed by measuring the initial joint strength of the sample mounted on the substrate and reflowed and by measuring the joint strength of the sample after the high temperature leaving test and the constant temperature and the humidity leaving test. This evaluation was compered with those of the usual other copper core balls electroplated with (Sn,Sn-Ag,Sn-Cu,Sn-Bi) and the Sn-Ag-Cu solder ball.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.71-71
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• 2009

Recently several LCD TV makers including Samsung, LG and Sony actively have released LED LCD TV models on market. LED LCD TV is just which applied LED BLUs so that its color contrast ratio fairly enhance up to 1 million:1 and its thickness minimize to a few mm. Even this aspect seems somewhat to be each panel maker's strategies for prior market occupations on whole TV market. Without regard to the reasons, we do obviously meet a new era of technically advanced LCD TV. However we have still lots of problems or issues which we must overcome technically including LED chip/packaging process, secondary optics treatment, heat managements and cost reduction issues. Here I would like to forecast market volume and trend of LED LCD TV first and then discuss above almost of technical issues and suggest their possible solutions. Even these solutions looks better technologies and if they may increase production cost significantly, we will not prefer to choice that technology since lower cost policy can open the market. Finally I'm trying to suggest how well LED, as future light source, can apply to future LCD TV technologies.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.377-378
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• 2006

Thermal management technology is a critical element in all new chip generations, caused by a power multiplication combined with a size reduction. A heat sink, mounted on a base plate, requires the use of special materials possessing both high thermal conductivity (TC) and a coefficient of thermal expansion (CTE) that matches semiconductor materials as well as certain packaging ceramics. In this study, nano tungsten coated copper powder has been developed with a wide range of compositions, 90W-10Cu to 10W-90Cu. Powder technologies were used to make samples to evaluate density, TC, and CTE. Measured TC lies among theoretical values predicted by several existing models.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.50-57
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• 2018

As devices have evolved, traditional flip chip bonding and recently commercialized thermocompression bonding techniques have been limited. Laser-assisted bonding is attracting attention as a technology that satisfies both the requirements of mass production and the yield enhancement of advanced packaging interconnections, which are weak points of these bonding technologies. The laser-assisted bonding technique can be applied not only to a two-dimensional bonding but also to a three-dimensional stacked structure, and can be applied to various types of device bonding such as electronic devices; display devices, e.g., LEDs; and sensors.

• Journal of the Semiconductor & Display Technology
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• v.17 no.1
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• pp.62-65
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• 2018

In the era of the 4th Industrial Revolution, IoT products of various and specialized fields are being developed and produced. Especially, the generation of the artificial intelligence, robotic technology Multilayer substrates and packaging technologies in the notebook, mobile device, display and semiconductor component industries are demanding the need for flexible materials along with miniaturization and thinning. To do this, this work use FCCL (Flexible Copper Clad Laminate), which is a flexible printed circuit board (PCB), to implement FPCB (Flexible PCB), COF (Chip on Film) Use is known to be essential. In this paper, I propose a transfer device which prevents the occurrence of scratches by analyzing the mechanism of wrinkle and scratch mechanism during the transfer process of thin film material in which the thickness increases while continuously moving in air or solution.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.135-142
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• 2024

Cu-Cu bonding, one of the key technologies in advanced packaging, enhances semiconductor chip performance, miniaturization, and energy efficiency by facilitating rapid data transfer and low power consumption. However, the quality of the interface bonding can significantly impact overall bond quality, necessitating strategies to quickly detect and classify in-process defects. This study presents a methodology for detecting defects in wafer junction areas from Scanning Acoustic Microscopy images using a ResNet-50 based deep learning model. Additionally, the use of the defect map is proposed to rapidly inspect and categorize defects occurring during the Cu-Cu bonding process, thereby improving yield and productivity in semiconductor manufacturing.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.75-81
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• 2015

In this paper, numerical analysis by finite element method and parameter design by the Taguchi method were used to reduce warpage of a two passive components embedded double side substrate for PoP(Package on Package). The effect of thickness of circuit layers (L1, L2) and thickness of solder resist (SR_top, SR_BTM) were analyzed with 4 variations and 3 levels(minimum, average and maximum thickness) to find optimized thickness conditions. Also, paste effect of solder resist on unit area of top surface was analyzed. Finally, experiments was carried out to prove numerical analysis and the Taguchi method. Based on the numerical and experimental results, it was known that circuit layer in ball side of substrate was the most severe determining deviation for reducing warpage. Buried circuit layer in chip side, solder resist and were insignificant effects on warpage relatively. However, warpage decreased as circuit layer in ball side thickness increased but effect of solder resist and circuit layer in chip side thickness were conversely.