• Proceedings of the KWS Conference
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• 2000.04a
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• pp.170-173
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• 2000

• Journal of Welding and Joining
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• v.29 no.1
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• pp.9-13
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• 2011

• Journal of KIISE:Software and Applications
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• v.31 no.6
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• pp.792-798
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• 2004

In this paper, we will introduce a new corner detector for the wafer die position recognition. The die position recognition procedure is necessary for WSCSP(Wafer Scale Chip Scale Packaging) technology, decide the accuracy of post-procedure. We present a hierarchical gray level corner detection method for the recognition of the die position from a wafer image. The new corner detector divides the corner region into many homocentric circles, and calculates the comer response and the angle of direction about each circle to get an accurate toner point. The new corner detector has a hierarchical structure so it can detect comer point more quickly than general gray level corner detector.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.1
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• pp.7-18
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• 1998

In the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as 1$\mu$m Al/0.2$\mu$m Pd/1$\mu$m Cu, laid under eutectic Pb/Sn solder were investigated with regard to their interfacial reactions and adhesion proper-ties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMCs) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1$\mu$m Al/0.2$\mu$m Ti/5$\mu$m Cu and 1$\mu$m Al/0.2$\mu$m ni/1$\mu$m Cu even after 4 solder reflows or 7 day aging at 15$0^{\circ}C$. In contrast 1$\mu$m Al/0.2$\mu$m Ti/1$\mu$m Cu and 1$\mu$mAl/0.2$\mu$m Pd/1$\mu$m 쳐 show poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. In this case thin 1$\mu$m Cu and 0.2$\mu$m Pd diffusion barrier layer were completely consumed by Cu-Sn and pd-Sn reaction.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.74-79
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• 2000

In an attempt to estimate the wetting properties of wettable metal layers by wetting balance method, an analysis of wetting curves of the coating layer was performed. Based on the analysis, wetting properties of UBM-coated Si-plate were estimated by the new wettability indices. The wetting curves of the one and both sides-coated UBM layers have the similar shape and show the similar tendency to the temperature. So the wetting property estimation of one side coating is possible with wetting balance method. For UBM of Si-chip, Cr/Cu/Au UBM is better than Ti/Ni/Au in the point of wetting time. At general reflow temperature, the wettability of high melting point solders(Sn-Sb, Sn-Ag) is better than that of few melting point ones(Sn-Bi, Sn-In).The contact angle of the one side coated plate to the solder can be calculated from the farce balance equation by measuring the static state force and the tilt angle.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.57-63
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• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.31-36
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• 2002

The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.19-25
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• 2000

Dielectric polymer films produced from benzocyclobutene (BCB) formulations (CYCLOTENE＊ family resins) are known to possess many desirable properties for microelectronic applications; for example, low dielectric constant and dissipation factor, low moisture absorption, rapid curing on hot plate without reaction by-products, minimum shrinkage in curing process, and no Cu migration issues. Recently, BCB-based products for thick film applications have been developed, which exhibited excellent dissipation factor and dielectric constant well into the GHz range, 0.002 and 2.50, respectively. Derived from these properties, the applications are developed in: bumping/wafer level packaging, Ga/As chip ILD, optical waveguide, flat panel display, and lately in BCB-coated Cu foil for build-up board. In this paper, we review the relevant properties of BCB, then the application areas in bumping/wafer level packaging and BCB-coated Cu foil for build-up board.