• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.763-768
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.

• 대한기계학회논문집A
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• 제28권4호
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• 한국표면공학회지
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• 제36권2호
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• pp.214-225
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• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.65-89
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• 2003

Next Highly sophisticated communication generation of the Advanced Electronics and Imaging processing society will require a vast information volume and super high speed signal transport and information instruction. This means that super high technology should be created for satisfying the demand. It's also required the high reliability of the communication system itself, It will be supported the new advanced packaging technology of the 3 Dimensional structured system and system integration technology. Here is introduced the new 3 Dimensional technology for IC nnd LSI packaging and Opt-electronics Packaging of ASET activity in Japan.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.127-133
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• 2001

솔더볼의 피로강도에 대한 솔더 조성의 영향을 조사하기 위하여 패키지 신뢰성 시험을 실시하였다. 공정조성 솔더, S $n_{62}$P $b_{36}$A $g_2$, S $n_{63}$P $b_{34.5}$A $g_2$S $b_{0.5}$ 솔더를 사용해 제조된 시편을 MRT Lv 2a 조건에서 전처리 후 TC 시험을 수행하였다. 제조 직후, 전처리 후, TC 후 각각에 대하여 전단강도를 측정하였으며, 미세 조직 사진을 얻었다. 또한, SEM과 EDX를 이용하여 파괴 기구에 대한 분석을 실시하였으며, 신뢰성 시험 후 전단강도의 저하에 대하여 논의하였다.다.

• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.9-17
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• 2003

In this paper, thermo-mechanical and rheological properties of NCPs (Non-Conductive Pastes) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermo-mechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature ($T_g$) and storage modulus at room temperature became higher. While, coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermo-mechanical properties such as modulus, CTE, and $T_g$. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국통신학회논문지
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• 제35권1B호
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• pp.62-67
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• 2010

본 연구는 다양한 산업 환경에 적용되는 RFID 태그 개발에 있어 RFID 태그 패키징 개발과 RFID 태그 플립칩(flip chip) 접합 방법이 산업 환경 맞춤형 RFID 태그 개발에 미치는 영향에 대해 분석하였다. RFID 태그 플립칩(flip chip) 접합은 와이어 접합(wire bonding), 초음파 접합(ultrasonic bonding), 열융착 접합(heat plate bonding), 레이저 접합(laser bonding)으로 구분되어 있으며, 이런 접합 방법은 다양한 RFID 태그 개발의 적용 환경에 따라 적합한 접합 방법이 있음을 본 연구를 통해서 알 수 있었다. 극고온, 극저온, 다습, 고내구성 등 다양한 산업 환경 중 극고온 환경에서의 RFID 태그 개발은 빛 에너지를 흡수하여 열 에너지로 전환하는 레이저 접합 방법과 직접적인 열 전달 방식인 열융착 접합 방법은 접속 재료인 ACF의 손상으로 인해 부적합하고, 와이어를 이용하여 직접 범프와 패턴을 연결하는 와이어 접합 방법이 적합함을 알 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.138-140
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• 2001

Fluxless flip chip bonding using plasma & ultrasonic wave was investigated in order to evaluate the effect of plasma & ultrasonic treatment on the bondability of the Sn-3.5wt%Ag solder bumped die to TSM-coated glass substrate. The $Ar+10%H_2plasma$ was effective in removing tin oxide on solder surface. The die shear strength of the plasma-treated Si-chip is higher than that of non-treated specimen but lower than that of specimen bonded with flux. The die shear strength with the bonding load at 25W ultrasonic power increased to 0.8N/bump for all bonding temperature but decreased above 1.0N/bump.

• Journal of Welding and Joining
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• 제25권2호
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• pp.76-81
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• 2007

Solder bumps have been used to interconnect the chip and substrate, and the size of the solder bump decreases below $100{\mu}m$ to accommodate higher packaging density. In order to fabricate solder bumps, a mold to chip transfer process is suggested in this work. Since the thin stainless steel mold is not wet by the solder, the molten solder is forced to fill the mold cavities with ultrasonic vibration. The solders within the mold cavities are transferred to the Cu pads on the polyimide film through reflow soldering.