• 마이크로전자및패키징학회지
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• 제11권1호
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• pp.29-36
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• 2004

초 박형 실리콘 칩을 이용하여 실리콘 칩들을 포함한 모듈 전체가 굽힘이 자유로운 유연 패키징 기술을 구현하였으며 bending test와 FEA를 통해 초 박형 실리콘 칩의 기계적 거동을 살펴보았다. 초박형 실리콘 칩(t<30$\mu\textrm{m}$)은 표면손상의 가능성을 배제하기 위해 KOH및 TMAH둥을 이용한 화학적 thinning 방법을 이용하여 제작되었으며 열압착 방식에 의해 $Kapton^{Kapton}$에 바로 실장 되었다. 실리콘칩과 $Kapton^\circledR$ 기판간의 단차가 적기 때문에 전기도금 방식으로 전기적 결선을 이를 수 있었다. 이러한 방식의 패키징은 이러한 공정은 flip chip 공정에 비해 공정 간단하고 wire 본딩과 달리 표면 단차 적어서 연성회로 기판을 비롯한 인쇄회로기판의 표면뿐만 아니라 기판 자체에 삽입이 가능하여 패키징 밀도 증가를 기대할 수 있으며 실질적인 실장 가능면적을 극대화 할 수 있다.

• 반도체디스플레이기술학회지
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• 제14권3호
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.155-162
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• 1999

A bare chip packaging technology by an encapsulated flip chip bonding on a build-up printed circuit board has emerged in 1991. Since then, it enabled a high density and low cost semiconductor packaging such as a direct chip bonding on mother board and high density surface mount components, such as BGA and CSP. This technology can respond to various requirements from applications and is considered to take over a main role of semiconductor packaging in the next decade.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.7-38
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• 2000

Performance, reliability, form factor drive flip chip use. BGAs and CSPs will provide stepping stone to FC DCA .Growing vendor infrastructure - Low cost, high density organic substrates -New generations of fluxes and underfills .Adhesives flip chip technology as a low cost flip chip alternatives -Low cost Au stud or Electroless Ni bumps -Reliable thermal cycling and electrical performance.

• 마이크로전자및패키징학회지
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• 제12권1호
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• pp.9-16
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• 2005

This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

• 마이크로전자및패키징학회지
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• 제6권4호
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• pp.61-71
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• 1999

통신분야에서 사용주파수대역의 증가, 제품의 소형화 및 가격경쟁력등의 요구에 따라 RF 소자의 패키징 기술도 플라스틱 패키지 대신에 flip chip interconnection, MCM(multichip module)등과 같은 고밀도 실장기술이 발전해가고 있다. 따라서, 본 논문은 최근 수년간 보고된 응용사례를 중심으로 RF flip chip의 기술적인 개발방향과 장점들을 분석하였고, RF 소자 및 시스템의 개발단계에 따른 적합한 적용기술을 제시하였다. RF flip chip의 기술동향을 요약하면, 1) RF chip배선은 microstrip 대신에 CPW 구조을 선택하며, 2) wafer back-side grinding을 하지 않아서 제조공정이 단순하고 wafer 파손이 적어 제조비용을 낮출 수 있고, 3) wire bonding 패키징에 비해 전기적인 특성이 우수하고 고집적의 송수신 모듈개발에 적합하다는 것이다. 그러나, CPW 배선구조의 RF flip chip 특성에 대한 충분한 연구가 필요하며 RF flip chip의 초기 개발 단계에서 flip chip interconnection 방법으로는 Au stud bump bonding이 적합할 것으로 제안한다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.71-72
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• 2012

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.17-23
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• 2013

신축성 전자패키징 기술개발을 위한 기초연구로서 Cu/Sn 범프에 CNT-Ag 복합패드를 형성한 칩을 이방성 전도접착제를 사용하여 플립칩 본딩한 후, CNT-Ag 복합패드의 유무 및 본딩압력에 따른 플립칩 접속부의 접속저항을 측정하였다. CNT-Ag 복합패드가 형성된 Cu/Sn 칩 범프를 25MPa과 50MPa의 본딩압력으로 플립칩 본딩한 시편들은 접속저항이 너무 높아 측정이 안되었으며, 100MPa의 본딩압력으로 플립칩 본딩한 시편은 $213m{\Omega}$의 평균 접속저항을 나타내었다. 이에 비해 CNT-Ag 복합패드가 없는 Cu/Sn 칩 범프를 사용하여 25MPa, 50 MPa 및 100 MPa의 본딩압력으로 플립칩 본딩한 시편은 각기 $1370m{\Omega}$, $372m{\Omega}$ 및 $112m{\Omega}$의 평균 접속저항을 나타내었다.