• 한국표면공학회지
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• 제36권2호
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• pp.214-225
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• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

• 마이크로전자및패키징학회지
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• 제8권2호
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 한국정밀공학회지
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• 제20권10호
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.15-16
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.821-822
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• 2011

• 대한화학회지
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• 제54권5호
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• pp.594-602
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• 2010

반도체의 경박단소화, 고밀도화에 따라 향후 반도체 패키지의 주 형태는 CSP(Chip Scale Package)가 될 것이다. 이러한 CSP에 사용되는 에폭시 수지 시스템의 흡습특성을 조사하기 위하여 에폭시 수지 및 충전재 변화에 따른 확산계수와 흡습율 변화를 조사하였다. 본 연구에 사용된 에폭시 수지로는 RE-304S, RE-310S, 및 HP-4032D를, 경화제로는 Kayahard MCD를, 경화촉매로는 2-methyl imidazole을 사용하였다. 충전재 크기 변화에 따른 에폭시 수지 성형물의 흡습특성을 조사하기 위하여 충전재로는 마이크로 크기 수준 및 나노 크기 수준의 구형 용융 실리카를 사용하였다. 이러한 에폭시 수지 성형물의 유리전이온도는 시차주사열량계를 이용하여 측정하였으며, 시간에 따른 흡습특성은 $85^{\circ}C$ and 85% 상대습도 조건하에서 항온항습기를 사용하여 측정하였다. 에폭시 수지 성형물의 확산계수는 Ficks의 법칙에 기초한 변형된 Crank 방정식을 사용하여 계산 하였다. 충전재를 사용하지 않은 에폭시 수지 시스템의 경우, 유리전이온도가 증가함에 따라 확산계수와 포화흡습율이 증가 하였으며 이는 유리전이온도 증가에 따른 에폭시 수지 성형물의 자유부피 증가로 설명하였다. 충전재를 사용한 경우, 충전재의 함량 증가에 따라 유리전이온도와 포화흡습율은 거의 변화가 없었으나, 확산계수는 충전재의 입자 크기에 따라 많은 변화를 보여주었다. 마이크로 크기 수준의 충전재를 사용한 경우 확산은 자유부피를 통하여 주로 이루어지나, 나노 크기 수준의 충전재를 사용한 에폭시 수지 성형물에서는 충전재의 표면적 증가에 따른, 수분 흡착의 상호작용을 통한 확산이 지배적으로 이루어진다고 판단된다.

• 한국생산제조학회지
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• 제24권4호
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• pp.448-454
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• 2015

In this paper, the band structural design that is typically in a line was arranged in a ring shape, so as to configure the high power LED lighting in such a way as to form a concentrated light distribution angle of less than 15 degrees. The parabolic aluminized reflector PAR38 that facilitates design using area and the area of the optical system to the same extent, applied a multiple light-source condenser lens optical system for the control of integration. The LED used here implemented a single linear light source using ans LED module with ans LED, flip-chip chip-scale package. The optical system was designed based on the energy star standard.