• BMB Reports
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• v.49 no.5
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• pp.247-248
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• 2016

Necroptosis is a well-known form of caspase-independent cell death. Necroptosis can be triggered by various extrinsic stimuli, including death ligands in the presence of receptorinteracting protein kinase 3 (RIPK3), a key mediator of necroptosis induction. Our recent studies have revealed that C-terminus HSC-70 interacting protein (CHIP), an E3 ligase, can function as an inhibitor of necroptosis. CHIP^−/− mouse embryonic fibroblast showed higher sensitivity to necrotic stimuli than wild-type mouse embryonic fibroblast cells. Deleterious effects of CHIP knockout MEFs were retrieved by RIPK3 depletion. We found that CHIP negatively regulated RIPK3 and RIPK1 by ubiquitylation- and lysosome- dependent degradation. In addition, CHIP^−/− mice showed postnatal lethality with intestinal defects that could be rescued by crossing with RIPK3^−/− mice. These results suggest that CHIP is a negative regulator of RIPK1 and RIPK3, thus inhibiting necroptosis.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.6
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• pp.118-126
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• 2000

In this study, geometrical similarity conditions for drills of various diameters are discussed. The effect of geometrical similarity on the chip shape and forces of different sized conventional drills has been experimentally confirmed. Drilling tests are carried out for SM45C by using the conventional HSS drills. The torque and thrust forces are measured and compared with those chip forms. Chip shape in drilling are affected by three factors being flow angle, side and up curl of the chip. It is found that the feedrate and drill diameter are more affected than cutting speed on the chip form and cutting forces. The similarity conditions gives easily to estimate the chip shape, the thrust and the torque for drills of different diameters.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.11
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• pp.64-70
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• 2003

This paper suggests a systematic methodology to predict chip forms using the experimental design technique and the neural network. Significant factors determined with ANOVA analysis are used as input variables of the neural network back-propagation algorithm. It has been shown that cutting conditions and cutting tool shapes have distinct effects on the chip forms, so chip breaking. Cutting tools are represented using the Z-map method, which differs from existing methods using some chip breaker parameters. After training the neural network with selected input variables, chip forms are predicted and compared with original chip forms obtained from experiments under same input conditions, showing that chip forms are same at all conditions. To verify the suggested model, one tool not used in training the model is chosen and input to the model. Under various cutting conditions, predicted chip forms agree well with those obtained from cutting experiments. The suggested method could reduce the cost and time significantly in designing cutting tools as well as replacing the“trial-and-error”design method.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.553-556
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• 1988

Recognition of IC chip pattern requires extraction of features, which have the information of vertex position and orientation. Edges are extracted and straightening algorithm is applied to the edges, so that lines are obtained. With these extracted data, the coordinate and orientation of all vertices are extracted and vertex-form matching is applied to the locally overlapped area of neighborhood frames to have global coordinate of IC chip.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• Molecular & Cellular Toxicology
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• v.2 no.4
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• pp.279-284
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• 2006

This paper describes the fabrication methods of a carbon nanotube (CNT) filter and a microdialysis chip. A CNT filter can help perform dialysis on a microfluidic chip. In this study, a membrane type of a CNT filter is fabricated and located in a microfluidic chip. The filter plays a role of a dialysis membrane in a microfluidic chip. In the fabrication process of a CNT filter, individual CNTs are entangled each other by amide bonding that is catalyzed by 1-Ethyl-3-(3-dimethylaminopropyl)carbodiimide (EDC) and N-hydroxysuccinimide (NHS). The chemically treated CNTs are shaped to form a CNT filter using a PDMS film-mold and vacuum filtering. Then, the CNT filter is sandwiched between PDMS substrates, and they are bonded together using a thin layer of PDMS prepolymer as adhesive. The PDMS substrates are fabricated to have a microchannel by standard photo-lithography technique.

• Journal of the Korean Society for Precision Engineering
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• v.7 no.2
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• pp.85-94
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• 1990

In automatic metal cuttings, the chip control is one of the serious problems. So the automatic detection of chip forms is essential to the chip control in automatic metal cuttings. Cutting experiments were carried out under the variety of cutting conditions (cutting speed, feed, depth of cut and tool geometry) and with workpiece made of steel (S45C), and cutting forces were measured in-processing by using a piezoelectric type Tool Dynamometer. In this report, the frequency analysis of dynamic components, the upper frequency distributions, the ratio of RMS values, the numbers of null point and the probability density were calculated from the dynamic componeents of cutting forces filtered through various band pass filters. Experimental results showed that computer chip form monitoring system based on the cutting forces was designed and simulated and that 6 type of chip forms could be detected while in-process machining.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1081-1090
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• 1988

A series of procedures using image processing techniques is presented for extracting layout information fast and automatically from chip images. CIF (caltech intermediate form) is chosen for representing such information. First, line-edges are extracted using a line-edge detector. Then, thinning and noise removal procedures follow. Subsequent procedures are vertex extraction and vertex grouping. Finally, CIF is extracted from the coordinates of the grouped vertices. In this paper, the final process is applied to only metal layer. In experiments, this processing scheme is shown to be very effective in extracting CIF.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.203-211
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• 2013

UHF RFID tag designers usually ndde the chip impedance and read power sensitivity value obtained when a tag chip is mounted on a chip pad. The chip impedance, however, is not able to be supplied by chip manufacturer, since the chip impedance is varied according to tag designs and fabrication processes. Instead, the chip makers mostly supply the chip impedances measured on the bare dies. This study proposes a chip impedance and read power sensitivity evaluation method which requires a few simple auxiliary and some RF measuring equipment. As it is impractical to measure the chip impedance directly at mounted chip terminals, some form test fixture is employed and the effect of the fixture is modeled and de-embeded to determine the chip impedance and the read power sensitivity. Validity and accuracy of the proposed de-embed method are examined by using commercial RFID tag chips as well as a capacitor and a resistor the value of which are known.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.41-47
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• 2011

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. Also, the need for high speed data transmission and reception coupled with the ever increasing demand for mobility in consumer devices has generated a great interest in low cost devices with smaller form-factors. The UWB BPF makes use of lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). In this paper, this filter shows 2.0 dB insertion loss and 15 dB return loss from 7.0 GHz to 9.0 GHz. To the best of our knowledge, the UWB band-pass-filter developed in this paper has the smallest size ($1.4\;mm{\times}1.2\;mm{\times}0.40\;mm$) while achieving equivalent electrical performance.