• 제목/요약/키워드: Chip Configuration

검색결과 113건 처리시간 0.026초

사물인터넷 디바이스의 집적회로 목적물과 소스코드의 유사성 분석 및 동일성 (Similarity Evaluation and Analysis of Source Code Materials for SOC System in IoT Devices)

  • 김도현;이규대
    • 한국소프트웨어감정평가학회 논문지
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    • 제15권1호
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    • pp.55-62
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    • 2019
  • 사물인터넷 디바이스의 소형화, 저전력화 요구는 프로그램을 단일 칩으로 구현하는 SOC 기술로 구현되고 있다. 불법 복제에 의한 저작권 분쟁은 반도체 칩에서도 증가하고 있으며, 디자인하우스의 칩 구현에서의 분쟁과 소스코드의 도용에 의한 칩 구현에 발생하고 있다. 그러나 최종 칩 구현은 디자인하우스에서 제작되기 때문에 저작권의 보호범위에서 어려움이 있다. 본 연구에서는 사물인터넷 디바이스의 집적회로에서 HDL 언어로 작성된 소스코드의 분쟁에서, 유사성을 판단하기 위한 분석방법과 유사성 판단의 기준을 설정하는 항목에 대해 다루었다. 특히 동일한 시방서를 기준으로 제작된 칩의 경우 동일한 구성과 코드 형태를 포함해야 하는 제작특성에서 유사성의 판단영역을 구분하는 내용에 대해서도 다룬다.

2.4-GHz Power Amplifier with Power Detector Using Metamaterial-Based Transformer-Type On-Chip Directional Coupler

  • Dang, Trung-Sinh;Tran, Anh-Dung;Lee, Bomson;Yoon, Sang-Woong
    • ETRI Journal
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    • 제35권3호
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    • pp.554-557
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    • 2013
  • This letter presents a power amplifier (PA) with an on-chip power detector for 2.4-GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.

공구 공작물간의 상대변위를 고려한 엔드밀링의 절삭공정 모델링 (Cutting Process Modeling of End-Milling in a Closed-Loop Configuration)

  • 황철현;조동우
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1995년도 추계학술대회 논문집
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    • pp.1059-1062
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    • 1995
  • In cutting system, relative displacement between rool and workpiece is very important. Even though there have been so many works for modeling cutting process of end-milling, most of them have considered only one displacement of either tool or workpiece instead of both. In this paper, the relative displacement between tool and workpiece is considered for modeling cutting process of end-milling using simple experimental modal analysis and cutting force simulation program is developed. In cutting force model, instantaneous uncut chip thickness model is used and Runge-Kutta method is used for the simulation of time varying cutting system.

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슈퍼박테리아 감염 치료를 위한 저전압 구동 플라즈마-온-칩 (Low Voltage Plasma-on-a-Chip for Inactivation of Superbacteria)

  • 임토우;황솔;김영민
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2015년도 제46회 하계학술대회
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    • pp.1249-1250
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    • 2015
  • We report a plasma-on-a-chip (POC) which provides a non-thermal atmospheric plasma for superbacteria infection treatment A three-electrode configuration allows an initiation carrier injection prior to a primary discharge, leading to a significant reduction in a breakdown voltage. A stable non-thermal argon plasma is generated using a pulsed glow discharge and inactivation of anti-biotic resistant bacteria, for example MRSA, is successfully demonstrated by exposing the bacteria to the argon plasma in a couple of minutes.

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Neuron Chip을 이용한 공기조화설비 제어모듈 개발 (A Novel Development of Distributed intelligent Control Module Based on the LonWorks Neuron Chip for Air handling Units in the Heating, Ventilating and Air Conditioning)

  • 홍원표;김동화;김중곤
    • 한국조명전기설비학회:학술대회논문집
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    • 한국조명전기설비학회 2003년도 학술대회논문집
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    • pp.251-257
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    • 2003
  • In this paper, a new distributed intelligent control module based on LonWorks fieldbus for air handling unit(AHU) of heating, ventilating and air-conditioning(HVAC) is proposed to replace with a conventional direct digital control(DDC) with 32 bit microprocessor. The proposed control architecture has a excellent features such as highly compact and flexible function design, a low priced smart front-end and reliable performance with various functions. This also addresses issues in control network configuration, logical design of field devices by S/W tool, Internet networking and electronic element installation. Experimental results showing the system performance are also included in this paper.

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Hybrid Multi-System-on-Chip Architecture as a Rapid Development Approach for a High-Flexibility System

  • Putra, Rachmad Vidya Wicaksana;Adiono, Trio
    • IEIE Transactions on Smart Processing and Computing
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    • 제5권1호
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    • pp.55-62
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    • 2016
  • In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

신경회로망칩(ERNIE)을 위한 학습모듈 설계 (Learning Module Design for Neural Network Processor(ERNIE))

  • 정제교;김영주;동성수;이종호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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    • pp.171-174
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    • 2003
  • In this paper, a Learning module for a reconfigurable neural network processor(ERNIE) was proposed for an On-chip learning. The existing reconfigurable neural network processor(ERNIE) has a much better performance than the software program but it doesn't support On-chip learning function. A learning module which is based on Back Propagation algorithm was designed for a help of this weak point. A pipeline structure let the learning module be able to update the weights rapidly and continuously. It was tested with five types of alphabet font to evaluate learning module. It compared with C programed neural network model on PC in calculation speed and correctness of recognition. As a result of this experiment, it can be found that the neural network processor(ERNIE) with learning module decrease the neural network training time efficiently at the same recognition rate compared with software computing based neural network model. This On-chip learning module showed that the reconfigurable neural network processor(ERNIE) could be a evolvable neural network processor which can fine the optimal configuration of network by itself.

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단방향 경로 스위칭 링을 위한 경로 제어 스위치 소자 (A Path Control Switch Chip for an Unidirectional Path Swithced Ring)

  • 이상훈
    • 한국통신학회논문지
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    • 제24권8A호
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    • pp.1245-1251
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    • 1999
  • 1.25Gb/s 처리용량의 디지털 신호들의 경로를 제어하는 스위치 소자가 COMPASS 툴로 설계되었고 0.8$\mu\textrm{m}$ CMOS 게이트 어레이로 LG 반도체에서 제작되었다. 이 소자는 초고속국가망의 전송노드 역할을 하는 SDH 전송 시스템에서 디지털 종속신호들의 자기복구동작을 가능하게 한다. 본 논문에서 제안한 경로 제어 스위치 소자는 SDH 선형 전송망과 단방향 링과 같은 환형 전송망에도 적용 가능한 구조로 설계되었다. 경로 제어 스위치 소자의 자기복구동작은 스위치내의 데이터 레지스터에 저장된 설정 데이터들을 변경시킴으로 이루어진다. SDH 전송시스템에의 적용시험 결과, 이 소자는 임의의 광선로 장애 시 즉시 복구가 가능함을 보여 주었으며 BER 10-11~10-12 정도로 양호하게 동작됨이 검증되었다. 2개의 동일한 혹은 그 이상의 스위치를 병렬구조로 구성하면 2.5Gb/s 혹은 그 이상의 처리용량도 얻을 수 있다.

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VoIP 시스템 칩 설계 및 기능 검증용 보드 개발 (The VoIP System on Chip Design and the Test Board Development for the Function Verification)

  • 소운섭;황대환;김대영
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2003년도 추계종합학술대회
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    • pp.990-994
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    • 2003
  • 본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 음성신호 접속 기능 및 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

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마이크로솔더링을 이용한 정전류다이오드 회로 자외선 LED 광원모듈 제작 (Fabrication Of Ultraviolet LED Light Source Module Of Current Limiting Diode Circuit By Using Flip Chip Micro Soldering)

  • 박종민;유순재;카완 안일
    • 한국전기전자재료학회논문지
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    • 제29권4호
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    • pp.237-240
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    • 2016
  • The improvement of irradiation intensity and irradiation uniformity is essential for large area and high power UVA light source application. In this study, large number of chips bonded by micro soldering technique were driven by low current, and current limiting diodes were configured to supply constant current to parallel circuits consisting of large number of series strings. The dimension of light source module circuit board was $350{\times}90mm^2$ and 16,650 numbers of 385 nm flip chip LEDs were used with a configuration of 90 parallel and 185 series strings. The space between LEDs in parallel and series strings were maintained at 1.9 mm and 1.0 mm distance, respectively. The size of the flip chip was $750{\times}750{\mu}m^2$ were used with contact pads of $260{\times}669{\mu}m^2$ size, and SAC (96.5 Sn/3.0 Ag/0.5 Cu) solder was used for flip chip bonding. The fabricated light source module with 7.5 m A supply current showed temperature rise of $66^{\circ}C$, whereas irradiation was measured to be $300mW/cm^2$. Inaddition, 0.23% variation of the constant current in each series string was demonstrated.