• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.183-186
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• 2015

This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Korean Journal of Metals and Materials
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• v.48 no.3
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.155-165
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• 2010

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.261-261
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• 2016

플래시 메모리 (flash memory)는 DRAM(dynamic racdom access memory)이나 SRAM(static random access memory)에 비해 소자의 구조가 매우 단순하기 때문에 집적도가 높아서 기기의 소형화가 가능하다는 점과 제조비용이 낮다는 장점을 가지고 있다. 또한, 전원을 차단하면 정보가 사라지는 DRAM이나 SRAM과 달리 전원이 꺼지더라도 저장된 정보가 지워지지 않는다는 특징을 가지고 있어서 ROM(read only memory)과 정보의 입출력이 자유로운 RAM의 장점을 동시에 가지기 때문에 활용도가 크다. 또한, 속도가 빠르고 소비전력이 작아서 USB 드라이브, 디지털 TV, 디지털 캠코더, 디지털 카메라, 휴대전화, 개인용 휴대단말기, 게임기 및 MP3 플레이어 등에 널리 사용되고 있다. 특히, 낸드(NAND)형의 플래시 메모리는 고집적이 가능하며 하드디스크를 대체할 수 있어 고집적 음성이나 화상 등의 저장용으로 많이 쓰이며 일정량의 정보를 저장해두고 작업해야 하는 휴대형 기기에도 적합하며 가격도 노어(NOR)형에 비해 저렴하다는 장점을 가진다. 최근에는 smart watch, wearable device 등과 같은 차세대 디스플레이 소자에 대한 관심이 증가함에 따라 투명하고 유연한 메모리 소자에 대한 연구가 다양하게 진행되고 있으며 유리나 플라스틱과 같은 기판 위에서 투명한 플래시 메모리를 형성하는 기술에 대한 관심이 높아지고 있다. 전하트랩형 (charge trap type) 플래시 메모리는 플로팅 게이트형 플래시 메모리와는 다르게 정보를 절연막 층에 저장하므로 인접 셀간의 간섭이나 소자의 크기를 줄일 수 있기 때문에 투명하고 유연한 메모리 소자에 적용이 가능한 차세대 플래시 메모리로 기대되고 있다. 전하트랩형 플래시메모리는 정보를 저장하기 위하여 tunneling layer, trap layer, blocking layer의 3층으로 이루어진 게이트 절연막을 가진다. 전하트랩 플래시 메모리는 게이트 전압에 따라서 채널의 전자가 tunnel layer를 통해 trap layer에 주입되어 정보를 기억하게 되는데, trap layer에 주입된 전자가 다시 채널로 빠져나가는 charge loss 현상이 큰 문제점으로 지적된다. 따라서 tunnel layer의 막질향상을 위한 다양한 열처리 방법들이 제시되고 있으며, 기존의 CTA (conventional thermal annealing) 방식은 상대적으로 높은 온도와 긴 열처리 시간을 가지고, RTA (rapid thermal annealing) 방식은 매우 높은 열처리 온도를 필요로 하기 때문에 플라스틱, 유리와 같은 다양한 기판에 적용이 어렵다. 따라서 본 연구에서는 기존의 열처리 방식보다 에너지 전달 효율이 높고, 저온공정 및 열처리 시간을 단축시킬 수 있는 마이크로웨이브 열처리(microwave irradiation, MWI)를 도입하였다. Tunneling layer, trap layer, blocking layer를 가지는 MOS capacitor 구조의 전하트랩형 플래시 메모리를 제작하여 CTA, RTA, MWI 처리를 실시한 다음, 전기적 특성을 평가하였다. 그 결과, 마이크로웨이브 열처리를 실시한 메모리 소자는 CTA 처리한 소자와 거의 동등한 정도의 우수한 전기적인 특성을 나타내는 것을 확인하였다. 따라서, MWI를 이용하면 tunnel layer의 막질을 향상시킬 뿐만 아니라, thermal budget을 크게 줄일 수 있어 차세대 투명하고 유연한 메모리 소자 제작에 큰 기여를 할 것으로 예상한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.6
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• pp.409-413
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• 2012

In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.