• Journal of Sensor Science and Technology
• /
• v.31 no.1
• /
• pp.41-44
• /
• 2022

In this study, we have fabricated and characterized vertical double-gate (DG) InGaAs tunnel field-effect-transistors (TFETs) with Al₂O₃/HfO₂ = 1/5 nm bi-layer gate dielectric by employing a top-down approach. The device exhibited excellent characteristics including a minimum subthreshold swing of 60 mV/decade, a maximum transconductance of 141 µS/㎛, and an on/off current ratio of over 10³ at 20℃. Although the TFETs were fabricated using a dry etch-based top-down approach, the values of DIBL and hysteresis were as low as 40 mV/V and below 10 mV, respectively. By evaluating the effects of constant voltage and hot carrier injection stress on the vertical DG InGaAs TFET, we have identified the dominant charge trapping mechanism in TFETs.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.20 no.6
• /
• pp.14-18
• /
• 2019

The conductivity of a semiconductor is primarily determined by the carriers. To achieve higher conductivity, the number of carriers should be high, and an energy trap level is created so that the carriers can cross the forbidden zone with low energy. Carriers have a crystalline binding structure, and interfacial mismatching tends to make them less conductive. In general, high-concentration doping is typically used to increase mobility. However, higher conductivity is also observed in non-orthogonal conjugation structures. In this study, the phenomena of higher conductivity and higher mobility were observed with space charge limiting current due to tunneling phenomena, which are different from trapping phenomena. In an atypical structure, the number of carriers is low, the resistance is high, and the on/off characteristics of capacitances are improved, thus increasing the mobility. ZTO thin film improved the on/off characteristics of capacitances after heat treating at $150^{\circ}C$. In charging and discharging tests, there was a time difference in the charge and discharging shapes, there was no distinction between n and p type, and the bonding structure was amorphous, such as in the depletion layer. The amorphous bonding structure can be seen as a potential barrier, which is also a source of space charge limiting current and causes conduction as a result of tunneling. Thus, increased mobility was observed in the non-structured configuration, and the conductivity increased despite the reduction of carriers.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.86-86
• /
• 2012

The new approaches for silicon solar cell of new concept have been actively conducted. Especially, solar cells with wire array structured radial p-n junctions has attracted considerable attention due to the unique advantages of orthogonalizing the direction of light absorption and charge separation while allowing for improved light scattering and trapping. One-dimenstional semiconductor nano/micro structures should be fabricated for radial p-n junction solar cell. Most of silicon wire and/or pillar arrays have been fabricated by vapour-liquid-solid (VLS) growth because of its simple and cheap process. In the case of the VLS method has some weak points, that is, the incorporation of heavy metal catalysts into the growing silicon wire, the high temperature procedure. We have tried new approaches; one is electrochemical etching, the other is noble metal catalytic etching method to overcome those problems. In this talk, the silicon pillar formation will be characterized by investigating the parameters of the electrochemical etching process such as HF concentration ratio of electrolyte, current density, back contact material, temperature of the solution, and large pre-pattern size and pitch. In the noble metal catalytic etching processes, the effect of solution composition and thickness of metal catalyst on the etching rate and morphologies of silicon was investigated. Finally, radial p-n junction wire arrays were fabricated by spin on doping (phosphor), starting from chemical etched p-Si wire arrays. In/Ga eutectic metal was used for contact metal. The energy conversion efficiency of radial p-n junction solar cell is discussed.

• Journal of Sensor Science and Technology
• /
• v.18 no.1
• /
• pp.48-53
• /
• 2009

$Eu^{2+}$-doped ${SrAl_2}{O_4}$ and $Eu^{2+}$, $Dy^{3+}$ co-doped ${SrAl_2}{O_4}$ phosphors have been synthesized by conventional solid state method. Photocurrent properties of $Eu^{2+}$ doped ${SrAl_2}{O_4}$ and $Eu^{2+}$, $Dy^{3+}$ co-doped ${SrAl_2}{O_4}$ phosphors, in order to elucidate $Dy^{3+}$ co-doping effect, during and after ceasing ultraviolet-ray (UV) irradiation have been investigated. The photocurrent of $Eu^{2+}$, $Dy^{3+}$ co-doped ${SrAl_2}{O_4}$ phosphors during UV irradiation was 4-times lower than that of $Eu^{2+}$-doped ${SrAl_2}{O_4}$ during UV irradiation, and 7-times higher than that of $Eu^{2+}$-doped ${SrAl_2}{O_4}$ after ceasing UV irradiation. The photocurrent results indicated that holes of charge carriers captured in hole trapping center during the UV irradiation and liberated after-glow process, and made clear that $Dy^{3+}$ of co-dopant acted as a hole trap. The photocurrent of ${SrAl_2}{O_4}$ showed a good proportional relationship to UV intensity in the range of $1{\sim}5mW/cm^2$, and $Eu^{2+}$-doped ${SrAl_2}{O_4}$ was confirmed to be a possible UV sensor.

• Journal of Information Display
• /
• v.9 no.4
• /
• pp.21-29
• /
• 2008

We studied both the wavelength and intensity dependent photo-responses (photofield-effect) in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs). During the a-IGZO TFT illumination with the wavelength range from $460\sim660$ nm (visible range), the off-state drain current $(I_{DS_off})$ only slightly increased while a large increase was observed for the wavelength below 400 nm. The observed results are consistent with the optical gap of $\sim$3.05eV extracted from the absorption measurement. The a-IGZO TFT properties under monochromatic illumination ($\lambda$=420nm) with different intensity was also investigated and $I_{DS_off}$ was found to increase with the light intensity. Throughout the study, the field-effect mobility $(\mu_{eff})$ is almost unchanged. But due to photo-generated charge trapping, a negative threshold voltage $(V_{th})$ shift is observed. The mathematical analysis of the photofield-effect suggests that a highly efficient UV photocurrent conversion process in TFT off-region takes place. Finally, a-IGZO mid-gap density-of-states (DOS) was extracted and is more than an order of magnitude lower than reported value for hydrogenated amorphous silicon (a-Si:H), which can explain a good switching properties observed for a-IGZO TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.45-49
• /
• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.10
• /
• pp.83-90
• /
• 1998

The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2010.05a
• /
• pp.54.2-54.2
• /
• 2010

최근까지는 주로 비정질 실리콘이 디스플레이의 채널층으로 상용화 되어왔다. 비정질 실리콘 기반의 박막 트랜지스터는 제작의 경제성 및 균일성을 가지고 있어서 널리 상용화되고 있다. 하지만 비정질 실리콘의 구조적인 문제인 낮은 전자 이동도(< $1\;cm^2/Vs$)로 인하여 디스플레이의 대면적화에 부적합하며, 광학적으로 불투명한 특성을 갖기 때문에 차세대 디스플레이의 응용에 불리한 점이 있다. 이런 문제점의 대안으로 현재 국내외 여러 연구 그룹에서 산화물 기반의 반도체를 박막 트랜지스터의 채널층으로 사용하려는 연구가 진행중이다. 산화물 기반의 반도체는 밴드갭이 넓어서 광학적으로 투명하고, 상온에서 증착이 가능하며, 비정질 실리콘에 비해 월등히 우수한 이동도를 가짐으로 디스플레이의 대면적화에 유리하다. 특히 Zinc Oxide의 경우, band gap이 3.4eV로써, transparent conductors, varistors, surface acoustic waves, gas sensors, piezoelectric transducers 그리고 UV detectors 등의 많은 응용에 쓰이고 있다. 또한, a-Si TFTs에 비해 ZnO-based TFTs의 경우 우수한 소자 성능과 신뢰성을 나타내며, 대면적 제조시 우수한 균일성 및 낮은 생산비용이 장점이다. 그러나 ZnO-baesd TFTs의 경우 일정한 bias 아래에서 threshold voltage가 이동하는 문제점이 displays의 소자로 적용하는데 매우 중요하고 문제점으로 여겨진다. 특히 gate insulator와 channel layer사이의 interface에서의 defect에 의한 charge trapping이 이러한 문제점들을 야기한다고 보고되어진다. 본 연구에서는 Zinc Oxide 기반의 박막 트랜지스터를 DC magnetron sputtering을 이용하여 상온에서 제작을 하였다. 또한, $Si_3N_4$ 기판 위에 electron cyclotron resonance (ECR) $O_2$ plasma 처리와 plasma-enhanced chemical vapor deposition (PECVD)를 통하여 $SiO_2$ 를 10nm 증착을 하여 interface의 개선을 시도하였다. 그리고 TFTs 소자의 출력 특성 및 전이 특성을 평가를 하였고, 소자의 field effect mobility의 값이 향상을 하였다. 또한 Temperature, Bias Temperature stability의 조건에서 안정성을 평가를 하였다. 이러한 interface treatment는 안정성의 향상을 시킴으로써 대면적 디스플레의 적용에 비정질 실리콘을 대체할 유력한 물질이라고 생각된다.

• ETRI Journal
• /
• v.31 no.6
• /
• pp.660-666
• /
• 2009

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Zn-oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below $200^{\circ}C$, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as $Si_3N_4$ and $Al_2O_3$, the electrical properties are analyzed. After post-annealing at $200^{\circ}C$ for 1 hour in an $O_2$ ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a $Si_3N_4$ IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogen-based bonds. From constant-current stress tests of $I_d$ = 3 ${\mu}A$, an IGZO-TFT with heat-treated $Si_3N_4$ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.6
• /
• pp.117-127
• /
• 1994

In this paper, electrical and reliability properties of N$_2$O oxides, grown at the temperature of 95$0^{\circ}C$ and 100$0^{\circ}C$ to 74$\AA$, and 82$\AA$. respectively, using NS12TO gas in a conventional furnace, have been compared with those of pure oxide grown at the temperature of 850 to 84$\AA$ using O$_2$ gas. Initial IS1gT-VS1gT characteristics of N$_2$O oxides were similar to those of pure oxide, and reliability properties of N$_2$O oxides, such as charge trapping, interface state density and leakage current at low electric field under F-N stress, were improved much better than those of pure oxide. But, with increasing capacitor area. TDDB characteristics of N$_2$O oxides were more degraded than those of pure oxide and this degradation of TDDB characteristics was more severe in 100$0^{\circ}C$ N$_2$Ooxide than in 95$0^{\circ}C$ N$_2$O oxide. The improvement of reliability properties excluding TDDB in N$_2$Ooxides was attributed to the hardness of the interface improved by nitrogen pile-up at the interface of Si/SiO$_2$, but on the other hand, the degradation of TDDB characteristics in N$_2$O oxides was obsered due to the increase of local thinning spots caused by excessive nitrogen at interface during the growth of N$_2$O oxides.