• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.56-63
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• 2008

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

• Journal of IKEEE
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• v.23 no.3
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• pp.1061-1067
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• 2019

In this paper, a highly integrated 3-channel DC-DC converter is designed using power transistor width scaling (PTWS). For positive voltage, $V_{POS}$, a boost converter is designed using the set-time variable pulse width modultaion (SPWM) dual-mode and PTWS to improve efficiency at light load. For negative voltage, $V_{NEG}$, a 0.5 x regulated inverting charge pump is designed with pulse skipping modulation (PSM) controller to reduce power consumption, and for an additional positive voltage, $V_{AVDD}$, a LDO circuit is designed. The proposed DC-DC converter has been designed using a $0.18{\mu}m$ BCDMOS process. Simulation results show that the proposed converter has power efficiency of 56%~90% for load current range of 1 mA~70 mA and output ripple voltage less than 5 mV at positive voltage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• ETRI Journal
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• v.33 no.6
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• pp.880-886
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• 2011

With the introduction of high-current 8-inch solar cells, conventional Schottky bypass diodes, usually adopted in photovoltaic (PV) panels to prevent the hot spot phenomenon, are becoming ineffective as they cause relatively high voltage drops with associated undue power consumption. In this paper, we present the architecture of an active circuit that reduces the aforementioned power dissipation by profitably replacing the bypass diode through a power MOS switch with its embedded driving circuitry. Experimental prototypes were fabricated and tested, showing that the proposed solution allows a reduction of the power dissipation by more than 70% compared to conventional Schottky diodes. The whole circuit does not require a dedicated DC power and is fully compatible with standard CMOS technologies. This enables its integration, even directly on the panel, thereby opening new scenarios for next generation PV systems.

• Journal of information and communication convergence engineering
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• v.3 no.1
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.215-216
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• 2008

In this paper, we describe a UHF-band CMOS fractional-N frequency synthesizer using a ring - type VCO. It has been designed using $0.18{\m}m$ CMOS technology. First, The newly designed charge-pump circuit includes an OTA for matching between the upper current and the lower current In addition, a ring - type VCO is also used for small chip sire. The simulation results show that the designed circuit has a phase noise of -109.53dBc/Hz at 1MHz offset and consumes 19.4mA from a 1.8V supply. The lock time is less than 30usec and the chip size is $0.45mm{\times}0.5mm$.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.5
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• pp.501-507
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• 2000

A nobel low-cost, simple and unity-power-factor electronic ballast is presented. The proposed electronic ballast employs a bypassing capacitor- and load networks composed of ballast capacitors and small charge pump capacitors as power factor correction circuit combined with the secondary winding of the transformer in the self-excited current-fed push-pull resonant inverter(CF-PPRI), resulting in cost-effectiveness and higher efficiency. By analyzing the princip1es of power factor correction mathematically, optimum design guidelines are presented. Since the lamps are used in power factor correction stage, the input power is automatically adjusted according to the number of the lamps.