• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.266-269
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.515-522
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both v voltage-fed and current-f,어 ek'Ctronic ballast. The proposed PFC circuits use valley-fil[(VF) type DClink s stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations d during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant c capaCltor In current-fed type, the charge pump capacitors are connc'Ctc'Cl with the additional second따y-side of t the power transformer. The measured PF is higher than 0.99 and THD is about 10% for all proposed PFC c circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for i implementing cost longrightarroweffective electronic ballast.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1899-1909
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• 2007

A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with $0.13{\mu}m$ triple-well DDI process, fabricated, and tested.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.665-666
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• 2008

Inserted HTS (high temperature superconducting) coil is promisingly expected as a solution for achievement of higher fields such as GHz scale NMR magnet. However, HTS magnet causes persistent current decay in the persistent current mode and this decay should be compensated in order to keep stable magnetic field. As a solution for the decay in the HTS magnets, we proposed a new type superconducting power supply, i.e., linear type magnetic flux pump (LTMFP). The LTMFP mainly consists of DC bias coil, 3-phase AC coil and superconducting Nb foil. The compensating current in closed superconductive circuit can be easily controlled by the intensity of 3-phase AC current and its frequency. In this study, it has been investigated that the flux pump can effectively charge the current for various frequencies according to the different load magnets.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.10
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• pp.1426-1431
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• 2015

Piezoelectric pump can be considered as R-C load and it needs something special driver because the output voltage does not become 0 even though the applied voltage is 0 with common converter. This operating system consists of fly-back converter to increase the input voltage and energy recovery inverter to apply square voltage to the piezoelectric pump. The energy recovery inverter can charge and discharge the energy of capacitive load. In this paper, to enhance performance of the driver, a few elements or circuits are added and modified. To drive the inverter safely, current limit resister is added and adjusted the value to valance the charging and discharging current. In addition, a current limit inductor is added to the input side to limit the input current and enhance the efficiency. Inductor only may make oscillation and another resister is added parallel to the inductor to solve this problem. The converter and inveter are assembled to one board for compactness. The appropriateness is proved with simulation and experiments.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.