• Transactions of the Korean Society of Mechanical Engineers B
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• v.38 no.11
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• pp.881-887
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• 2014

This paper presents numerical study on flow and heat transfer characteristics in micro-gap plate heat exchanger. In particular, we investigate the effect of flow inertia on the flow distribution from single main channel to multiple parallel micro-gaps. The flow regime of the main channel is varied from laminar regime (Reynolds number of 100) to turbulent regime (Reynolds number of 10000) by changing the flow rate, and non-uniformity of the flow distribution and temperature field is evaluated quantitatively based on the standard deviation. The flow distribution is found to be significantly affected by not only the header design but also the flow rate of the main channel. It is also observed that the non-uniformity of the temperature field has its maximum at the intermediate flow regime.

• Geophysics and Geophysical Exploration
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• v.2 no.2
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• pp.77-85
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• 1999

The 3-D seismic research vessel, Tamhae II, was built to raise up the probability of the hydrocarbon discovery in the Korean continental shelf and the first test survey was completed in the East Sea. During the survey, the 240 channel 2-D marine seismic data were acquired by the Korean flag vessel for the first time. Tamhae II has been equipped with source, receiver, recording equipment, and navigation equipment as well as an onboard processing system. The source is composed of four subarrays and each subarray has six airguns. Total airgun volume is 4578 $in^3$. The receiver consists of two sets of 3 km long 240 channel streamer. In the first survey, the successful acquisition of 2-D seismic data was accomplished. From the result of the data processing, we confirmed that the high quality seismic data were acquired. For the high quality data acquisition, technology of survey design and planning, operation of vessel and equipments and systematic quality control should be developed.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.10
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• pp.2585-2596
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• 1994

Many particle filled materials like Poweder/Binder mixtures for poweder injection moldings, have complicated rheological behaviors such as an yield stress and slip phenomena. In the present study, numerical simulation programs via a finite element method and a finite difference method were developed for the quasi-three-dimensional flows and the two-dimensional flow models, respectively, with the slip phenomena taken into account in terms of a slip velocity. In order to qualitatively understand the slip effects, typical numerical results such as vector plots, pressure contours in the cross-channel plane, and isovelocity controus for the down-channel direction were discussed with respect to various slip coefficients. Slip velocities along the boudary surfaces were also investigated to find the effects of the slip coefficient and processing conditions on the overall flow behavior. Based on extensive numerical calculations varying the slip coefficients, pressure gradient, aspect ratio, and power law index, the screw characteristics of the extrusion process were studied in particular with comparisons between the slip model and non-slip model.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.31.1-31.1
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• 2010

Various ZnO nanostructures were synthesized and ZnO nanostructure-based self-assembled transistors were fabricated. Compared to spindle and flower like nanostructure, the ZnO nanorod (NR) structure showed much stronger gate controllability, and greatly enhanced device performance, demonstrating that this structural variation leads to significant differences of the nanostructure network-based device performance. Also, patterned dry transfer-printing technique that can generate monolayer-like percolating networks of ZnO NRs has been developed. The method exploits the contact area difference between NR-NR and NR-substrate, rather than elaborate tailoring of surface chemistry or energetic. The devices prepared by the transferring method exhibited on/off current ratio, and mobility of ${\sim}2.7{\times}10^4$ and ${\sim}1.03\;cm^2/V{\cdot}s$, respectively. Also, they exhibited showing lower off-current and stronger gate controllability due to defined-channel between electrodes and monolayer-like network channel configuration. With multilayer stacks of nanostructures on stamp, the monolayer-like printing can be repeated many times, possibly on large area substrate, due to self-regulating printing characteristics. The method may enable high-performance macroelectronics with materials that have high aspect ratio.

• Korean Journal of Metals and Materials
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• v.47 no.11
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• pp.699-706
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• 2009

Deformation behavior of pure aluminum during equal channel angular pressing (ECAP) was simulated using a three-dimensional version of the finite element method in conjunction with a constitutive model based on the dislocation density and cell evolution. The three-dimensional finite element analyses for the prediction of microstructural features, such as the variation of the dislocation density and the cell size with the number of ECAP, are reported. The calculated stress and strain and their distributions are also investigated for the route Bc ECAP processed pure aluminum. The results of finite element analyses are found to be in good agreement with experimental results for the dislocation cell size. Due to the accumulation of strain throughout the workpiece and an overall trend to saturation in cell size, a decrease of the difference in cell size with the number of passes (1~4) was predicted.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.2
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• pp.99-104
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• 2021

Ion-beam sputtering (IBS) was used to deposit semiconducting IZTO (indium zinc tin oxide) thin films onto heavily-doped Si substrates using a sintered ceramic target with the nominal composition In0.4Zn0.5Sn0.1O1.5, which could work as a channel layer for oxide TFT (oxide thin film transistor) devices. The crystallization behavior and electrical properties were examined for the films in terms of deposition parameters, i.e. target tilt angle and substrate temperature during deposition. The thickness uniformity of the films were examined using a stylus profilometer. The observed difference in electrical properties was not related to the degree of crystallization but to the deposition temperature which affected charge carrier concentration (n), electrical resistivity (ρ), sheet resistance (Rs), and Hall mobility (μH) values of the films.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.

• Electrical & Electronic Materials
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• v.9 no.2
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• pp.174-179
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• 1996

We present a new physically based analytical equation for electron effective mobility in MOS inversion layers. The new semi-empirical model is accounting expicitly for surface roughness scattering and screened Coulomb scattering in addition to phonon scattering. This model shows excellent agreement with experimentally measured effective mobility data from three different published sources for a wide range of effective transverse field, channel doping and temperature. By accounting for screened Coulomb scattering due to doping impurities in the channel, our model describes very well the roll-off of effective mobility in the low field (threshold) region for a wide range of channel doping level (Na=3.0*10$^{14}$ - 2.8*10$^{18}$ cm$^{-3}$ ).

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.