• Journal of Electrical Engineering and Technology
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• 제1권3호
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• pp.396-405
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• 2006

The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

• The Korean Journal of Physiology and Pharmacology
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• 제2권4호
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• pp.529-539
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• 1998

The effects of membrane surface charge originated from lipid head groups on ion channels were tested by analyzing the activity of single large conductance $Ca^{2+}-activated\;K^+$ (maxi K) channel from rat skeletal muscle. The conductances and open-state probability ($P_o$) of single maxi K channels were compared in three types of planar lipid bilayers formed from a neutral phosphatidylethanolamine (PE) or two negatively-charged phospholipids, phosphatidylserine (PS) and phosphatidylinositol (PI). Under symmetrical KCl concentrations $(3{\sim}1,000\;mM)$, single channel conductances of maxi K channels in charged membranes were $1.1{\sim}1.7$ times larger than those in PE membranes, and the differences were more pronounced at the lower ionic strength. The average slope conductances at 100 mM KCl were $251{\pm}9.9$, $360{\pm}8.7$ and $356{\pm}12.4$ $(mean{\pm}SEM)$ pS in PE, PS and PI membranes respectively. The potentials at which $P_o$ was 1/2, appeared to have shifted left by 40 mV along voltage axis in the membranes formed with PS or PI. Such shift was consistently seen at pCa 5, 4.5, 4 and 3.5. Estimation of the effect of surface charge from these data indicated that maxi K channels sensed the surface potentials at a distance of $8{\sim}9\;{\AA}$ from the membrane surface. In addition, similar insulation distance ($7{\sim}9\;{\AA}$) of channel mouth from the bilayer surface charge was predicted by a 3-barrier-2-site model of energy profile for the permeation of $K^+$ ions. In conclusion, despite the differences in structure and fluidity of phospholipids in bilayers, the activities of maxi K channels in two charged membranes composed of PS or PI were strikingly similar and larger than those in bilayers of PE. These results suggest that the enhancement of conductance and $P_o$ of maxi channels is mostly due to negative charges in the phospholipid head groups.

• Advances in nano research
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• 제3권1호
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Journal of information and communication convergence engineering
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• 제4권2호
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• pp.84-87
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• 2006

Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

• 한국전기전자재료학회논문지
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• 제27권7호
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• pp.438-442
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• 2014

Channel length dependence of NBTI (negative bias temperature instablilty) and CHC (channel hot carrier) characteristics in PMOSFET is studied. It has been considered that HC lifetime of PMOSFET is larger than NBTI lifetime. However, it is shown that CHC degradation is greater than NBTI degradation for PMOSFET with short channel length. 1/f noise and charge pumping measurement are used for analysis of these degradations.

• 전기전자학회논문지
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• 제27권3호
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• pp.303-307
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• 2023

본 논문은 Buried Channel Array Transistor(BCAT) 소자의 Oxide 내부에 Total Ionizing Dose(TID) effects으로 인한 Electron-Hole Pair의 생성이 유도되어, Oxide 계면의 Hole Trap Charge의 증가에 따른 누설전류의 증가와 문턱 전압의 변화를 기존에 제안한 Partial Isolation Buried Channel Array Transistor(Pi-BCAT)구조와 비교 시뮬레이션 하여, Pi-BCAT 소자의 증가한 Oxide 면적과 상관없이 변화한 누설전류와 문턱 전압에서의 특성이 비대칭 도핑 BCAT 구조보다 우수함을 보여 준다.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• 전력전자학회논문지
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• 제26권1호
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• pp.66-73
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• 2021

This study presents a novel four-channel light-emitting diode (LED) current balancing topology using a current-fed hybrid quasi-Z-source converter. With the proposed structure, currents flowing through four LED strings are automatically balanced owing to the charge (amp-sec) balance condition on capacitors. Thus, automatic current balancing of the proposed driver is simple and precise. In addition, the proposed LED driver uses only one active switch and three diodes. The operating principle and characteristics of the proposed four-channel LED driver are analyzed in detail. To verify the operation of the proposed LED driver, a prototype is built and tested with different numbers of LEDs.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2006년도 춘계종합학술대회
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• pp.894-897
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• 2006

Spatial distribution of injected electrons and holes is evaluated by using single-junction charge pumping technique in SONOS(Poly-silicon/Oxide/Nitride/Oxide/Silicon) memory cells. Injected electron are limited to length of ONO(Oxide/Nitride/oxide) region in locally ONO stacked cell, while are spread widely along with channel in fully ONO stacked cell. Hot-holes are trapped into the oxide as well as the ONO stack in locally ONO stacked cell.

• Journal of Electrical Engineering and Technology
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• 제1권2호
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• pp.233-236
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• 2006

A 3-D numerical simulation of a buried-channel CCD (Charge Coupled Device) with a deep depletion has been performed to investigate its electrical and physical behaviors. Results are presented for a deep depletion CCD (EEV CCD12; JET-X CCD) fabricated on a high-resistivity $(1.5k\Omega-cm)\;65{\mu}m$ thick epi-layer, on a $550{\mu}m$ thick p+ substrate, which is optimized for X-ray detection. Accurate predictions of the Potential minimum and barrier height of a CCD Pixel as a function of mobile electrons are found to give good charge transfer. The depletion depth approximation as a function of gate and substrate bias voltage provided average errors of less than 6%, compared with the results estimated from X-ray detection efficiency measurements. The result obtained from the transient simulation of signal charge movement is also presented based on 3-Dimensional analysis.