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Simulation of Characteristics Analysis by Total Ionizing Dose Effects in Partial Isolation Buried Channel Array Transistor

부분분리 매립 채널 어레이 트랜지스터의 총 이온화 선량 영향에 따른 특성 해석 시뮬레이션

  • Je-won Park (Department of ICT Convergence System Engineering, Chonnam National University) ;
  • Myoung-Jin Lee (Department of ICT Convergence System Engineering, Chonnam National University)
  • Received : 2023.08.29
  • Accepted : 2023.09.20
  • Published : 2023.09.30

Abstract

In this paper, the creation of an Electron-Hole Pair due to Total Ionizing Dose (TID) effects inside the oxide of a Buried Channel Array Transistor (BCAT) device is induced, resulting in an increase in leakage current and threshold due to an increase in hole trap charge at the oxide interface. By comparing and simulating changes in voltage with the previously proposed Partial Isolation Buried Channel Array Transistor (Pi-BCAT) structure, the characteristics in leakage current and threshold voltage changed regardless of the increased oxide area of the Pi-BCAT device, compared to the asymmetrically doped BCAT structure. It shows superiority.

본 논문은 Buried Channel Array Transistor(BCAT) 소자의 Oxide 내부에 Total Ionizing Dose(TID) effects으로 인한 Electron-Hole Pair의 생성이 유도되어, Oxide 계면의 Hole Trap Charge의 증가에 따른 누설전류의 증가와 문턱 전압의 변화를 기존에 제안한 Partial Isolation Buried Channel Array Transistor(Pi-BCAT)구조와 비교 시뮬레이션 하여, Pi-BCAT 소자의 증가한 Oxide 면적과 상관없이 변화한 누설전류와 문턱 전압에서의 특성이 비대칭 도핑 BCAT 구조보다 우수함을 보여 준다.

Keywords

Acknowledgement

This research was supported by the BK21 FOUR Program(Fostering Outstanding Universities for Research, 519999 1714138) funded by the Ministry of Education (MOE, Korea) and National Research Foundation of Korea(NRF). This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the ICAN(ICT Challenge and Advanced Network of HRD) program (IITP-2023-RS-2022-00156385) supervised by the IITP (Institute of Information & Communications Technology Planning & Evaluation). This study was financially supported by Chonnam National University (Grant number: 2023-0149) The EDA tool was supported by the IC Design Education Center (IDEC), South Korea.

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